Attachment 'controller.c'
Download 1 /*----------------------------------------------------------------------*/
2 /* */
3 /* ------------------- */
4 /* */
5 /* LIGO */
6 /* */
7 /* THE LASER INTERFEROMETER GRAVITATIONAL WAVE OBSERVATORY. */
8 /* */
9 /* (C) The LIGO Project, 2005. */
10 /* */
11 /* */
12 /* */
13 /* California Institute of Technology */
14 /* LIGO Project MS 18-34 */
15 /* Pasadena CA 91125 */
16 /* */
17 /* Massachusetts Institute of Technology */
18 /* LIGO Project MS 20B-145 */
19 /* Cambridge MA 01239 */
20 /* */
21 /*----------------------------------------------------------------------*/
22
23 #include <rtl_time.h>
24 #include <fcntl.h>
25 #include <pthread.h>
26 #include <unistd.h>
27 #include <sys/mman.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <semaphore.h>
31 #include <linux/slab.h>
32 #include <drv/cdsHardware.h>
33 #include "inlineMath.h"
34 #include "feSelectHeader.h"
35 #include <string.h>
36
37 #ifndef NUM_SYSTEMS
38 #define NUM_SYSTEMS 1
39 #endif
40
41 #define INLINE inline
42 #define MMAP_SIZE (64*1024*1024 - 5000)
43 char *_epics_shm; /* Ptr to computer shared memory */
44 char *_ipc_shm; /* Ptr to inter-process communication area */
45 #if defined(SHMEM_DAQ)
46 char *_daq_shm; /* Ptr to frame builder comm shared mem area */
47 int daq_fd; /* File descriptor to share memory file */
48 #endif
49
50 long daqBuffer; /* Address for daq dual buffers in daqLib.c */
51 sem_t irqsem; /* Semaphore if in IRQ mode. */
52 CDS_HARDWARE cdsPciModules; /* Structure of hardware addresses */
53 volatile int vmeDone = 0;
54 volatile int stop_working_threads = 0;
55
56 #include "msr.h"
57 #include "fm10Gen.h" /* CDS filter module defs and C code */
58 #include "feComms.h" /* Lvea control RFM network defs. */
59 #include "daqmap.h" /* DAQ network layout */
60 extern unsigned int cpu_khz;
61 #define CPURATE (cpu_khz/1000)
62 #define ONE_PPS_THRESH 2000
63
64 // #include "fpvalidate.h" /* Valid FP number ck */
65 #ifndef NO_DAQ
66 #include "drv/gmnet.h"
67 #include "drv/fb.h"
68 #include "drv/myri.h"
69 #include "drv/daqLib.c" /* DAQ/GDS connection */
70 #endif
71 #include "drv/map.h"
72 #include "drv/epicsXfer.c" /* Transfers EPICS data to/from shmem */
73
74 #ifdef SERVO256K
75 #define CYCLE_PER_SECOND (2*131072)
76 #define CYCLE_PER_MINUTE (2*7864320)
77 #define DAQ_CYCLE_CHANGE (2*8000)
78 #define END_OF_DAQ_BLOCK (2*8191)
79 #define DAQ_RATE (2*8192)
80 #define NET_SEND_WAIT (2*655360)
81 #define CYCLE_TIME_ALRM 4
82 #endif
83 #ifdef SERVO128K
84 #define CYCLE_PER_SECOND 131072
85 #define CYCLE_PER_MINUTE 7864320
86 #define DAQ_CYCLE_CHANGE 8000
87 #define END_OF_DAQ_BLOCK 8191
88 #define DAQ_RATE 8192
89 #define NET_SEND_WAIT 655360
90 #define CYCLE_TIME_ALRM 7
91 #endif
92 #ifdef SERVO64K
93 #define CYCLE_PER_SECOND (2*32768)
94 #define CYCLE_PER_MINUTE (2*1966080)
95 #define DAQ_CYCLE_CHANGE (2*1540)
96 #define END_OF_DAQ_BLOCK (2*2047)
97 #define DAQ_RATE (DAQ_16K_SAMPLE_SIZE*4)
98 #define NET_SEND_WAIT (2*81920)
99 #define CYCLE_TIME_ALRM 15
100 #define DAC_START_DELAY 5
101 #endif
102 #ifdef SERVO32K
103 #define CYCLE_PER_SECOND 32768
104 #define CYCLE_PER_MINUTE 1966080
105 #define DAQ_CYCLE_CHANGE 1540
106 #define END_OF_DAQ_BLOCK 2047
107 #define DAQ_RATE (DAQ_16K_SAMPLE_SIZE*2)
108 #define NET_SEND_WAIT (2*81920)
109 #define CYCLE_TIME_ALRM 30
110 #define DAC_START_DELAY 10
111 #endif
112
113 #ifdef SERVO16K
114 #define CYCLE_PER_SECOND 16384
115 #define CYCLE_PER_MINUTE 983040
116 #define DAQ_CYCLE_CHANGE 770
117 #define END_OF_DAQ_BLOCK 1023
118 #define DAQ_RATE DAQ_16K_SAMPLE_SIZE
119 #define NET_SEND_WAIT 81920
120 #define CYCLE_TIME_ALRM 60
121 #define DAC_START_DELAY 40
122 #endif
123 #ifdef SERVO2K
124 #define CYCLE_PER_SECOND 2048
125 #define CYCLE_PER_MINUTE 122880
126 #define DAQ_CYCLE_CHANGE 120
127 #define END_OF_DAQ_BLOCK 127
128 #define DAQ_RATE DAQ_2K_SAMPLE_SIZE
129 #define NET_SEND_WAIT 10240
130 #define CYCLE_TIME_ALRM 487
131 #define DAC_START_DELAY 468
132 #endif
133
134 #ifndef NO_DAQ
135 DAQ_RANGE daq; /* Range settings for daqLib.c */
136 int numFb = 0;
137 int fbStat[2] = {0,0};
138 #endif
139
140 rtl_pthread_t wthread;
141 rtl_pthread_t wthread1;
142 rtl_pthread_t wthread2;
143 int wfd, ipc_fd;
144
145 /* ADC/DAC overflow variables */
146 int overflowAdc[4][32];;
147 int overflowDac[4][16];;
148 int overflowAcc = 0;
149
150 float *testpoint[20];
151
152
153 CDS_EPICS *pLocalEpics; /* Local mem ptr to EPICS control data */
154
155
156 /* 1/16 sec cycle counters for DAQS and ISC RFM IPC */
157 int subcycle = 0; /* Internal cycle counter */
158 unsigned int daqCycle; /* DAQS cycle counter */
159
160 int firstTime; /* Dummy var for startup sync. */
161
162 FILT_MOD dsp[NUM_SYSTEMS]; /* SFM structure. */
163 FILT_MOD *dspPtr[NUM_SYSTEMS]; /* SFM structure pointer. */
164 FILT_MOD *pDsp[NUM_SYSTEMS]; /* Ptr to SFM in shmem. */
165 COEF dspCoeff[NUM_SYSTEMS]; /* Local mem for SFM coeffs. */
166 VME_COEF *pCoeff[NUM_SYSTEMS]; /* Ptr to SFM coeffs in shmem */
167 double dWord[MAX_ADC_MODULES][32];
168 unsigned int dWordUsed[MAX_ADC_MODULES][32];
169 double dacOut[MAX_DAC_MODULES][16];
170 unsigned int dacOutUsed[MAX_DAC_MODULES][16];
171 int dioInput[MAX_DIO_MODULES];
172 int dioOutput[MAX_DIO_MODULES];
173 int rioInput[MAX_DIO_MODULES];
174 int rioOutput[MAX_DIO_MODULES];
175 int rioOutputHold[MAX_DIO_MODULES];
176 int rioInput1[MAX_DIO_MODULES];
177 int rioOutput1[MAX_DIO_MODULES];
178 int rioOutputHold1[MAX_DIO_MODULES];
179 unsigned int CDO32Input[MAX_DIO_MODULES];
180 unsigned int CDO32Output[MAX_DIO_MODULES];
181 int clock16K = 0;
182 double cycle_gps_time = 0.; // Time at which ADCs triggered
183 double cycle_gps_event_time = 0.; // Time at which ADCs triggered
184 unsigned int cycle_gps_ns = 0;
185 unsigned int cycle_gps_event_ns = 0;
186 unsigned int gps_receiver_unlocked = 1; // Lock/unlock flag for GPS time card
187
188 double getGpsTime(unsigned int *);
189 #include "./feSelectCode.c"
190
191 char daqArea[2*DAQ_DCU_SIZE]; /* Space allocation for daqLib buffers */
192
193
194 #ifdef OVERSAMPLE
195
196 /* Oversamping base rate is 64K */
197 /* Coeffs for the 2x downsampling (32K system) filter */
198 static double feCoeff2x[9] =
199 {0.053628649721183,
200 -1.25687596603711, 0.57946661417301, 0.00000415782507, 1.00000000000000,
201 -0.79382359542546, 0.88797791037820, 1.29081406322442, 1.00000000000000};
202 /* Coeffs for the 4x downsampling (16K system) filter */
203 static double feCoeff4x[9] =
204 {0.014805052402446,
205 -1.71662585474518, 0.78495484219691, -1.41346289716898, 0.99893884152400,
206 -1.68385964238855, 0.93734519457266, 0.00000127375260, 0.99819981588176};
207
208 /* Coeffs for the 32x downsampling filter (2K system) */
209 static double feCoeff32x[9] =
210 {0.0001104130574447,
211 -1.97018349613882, 0.97126719875540, -1.99025960812101, 0.99988962634797,
212 -1.98715023886379, 0.99107485707332, 2.00000000000000, 1.00000000000000};
213
214
215 double dHistory[96][40];
216 double dDacHistory[96][40];
217
218 #if 0
219 #ifdef SERVO2K
220 #define OVERSAMPLE_TIMES 32
221 #define FE_OVERSAMPLE_COEFF feCoeff32x
222 #elif SERVO16K
223 #define OVERSAMPLE_TIMES 4
224 #define FE_OVERSAMPLE_COEFF feCoeff4x
225 #elif SERVO32K
226 #define OVERSAMPLE_TIMES 2
227 #define FE_OVERSAMPLE_COEFF feCoeff2x
228 #else
229 #error Unsupported system rate when in oversampling mode: only 2K, 16K and 32K are supported
230 #endif
231 #endif
232
233 #else
234
235 #define OVERSAMPLE_TIMES 1
236 #endif
237
238 #define ADC_SAMPLE_COUNT (0x20 * OVERSAMPLE_TIMES)
239 #define ADC_DMA_BYTES (0x80 * OVERSAMPLE_TIMES)
240
241 // Whether run on internal timer (when no I/O cards found)
242 int run_on_timer = 0;
243
244 // Initial diag reset flag
245 int initialDiagReset = 1;
246
247 // DIAGNOSTIC_RETURNS_FROM_FE
248 #define FE_NO_ERROR 0x0
249 #define FE_SYNC_ERR 0x1
250 #define FE_ADC_HOLD_ERR 0x2
251 #define FE_FB0_NOT_ONLINE 0x4
252 #define FE_PROC_TIME_ERR 0x8
253 #define FE_ADC_SYNC_ERR 0xf0
254 #define FE_FB_AVAIL 0x1
255 #define FE_FB_ONLINE 0x2
256 #define FE_MAX_FB_QUE 0x10
257
258 #if 0
259 // **************************************************************************
260 // Interrupt handler if using interrupts for ADC module
261 // **************************************************************************
262 unsigned int intr_handler(unsigned int irq, struct rtl_frame *regs)
263 {
264 unsigned int status;
265 unsigned char sid;
266 /* pend this IRQ so that the general purpose OS gets it, too */
267 rtl_global_pend_irq(irq);
268
269
270 /*
271 * Do any interrupt context handling that must be done right away.
272 * This code is not running in a RTLinux thread but in an
273 * "interrupt context".
274 */
275
276 adcPtr->INTCR = 0x3;
277
278
279
280 /*
281 * Wake up the thread so it can handle any processing for this irq
282 * that can be done in a RTLinux thread and doesn't need to be done in
283 * an "interrupt context".
284 */
285 sem_post( &irqsem );
286
287 /* Reenable the hardware IRQ. (Not the software IRQ the GPOS now has. */
288 rtl_hard_enable_irq(irq);
289 return 0;
290 }
291 #endif
292
293
294 static double getGpsTime1(unsigned int *ns, int event_flag) {
295 double the_time = 0.0;
296
297 if (cdsPciModules.gps) {
298 // Sample time
299 if (event_flag) {
300 //cdsPciModules.gps[1] = 1;
301 } else {
302 cdsPciModules.gps[0] = 1;
303 }
304 // Read seconds, microseconds, nanoseconds
305 unsigned int time0;
306 unsigned int time1;
307 if (event_flag) {
308 time0 = cdsPciModules.gps[SYMCOM_BC635_EVENT0/4];
309 time1 = cdsPciModules.gps[SYMCOM_BC635_EVENT1/4];
310 } else {
311 time0 = cdsPciModules.gps[SYMCOM_BC635_TIME0/4];
312 time1 = cdsPciModules.gps[SYMCOM_BC635_TIME1/4];
313 }
314 gps_receiver_unlocked = !!(time0 & (1<<24));
315 unsigned int msecs = 0xfffff & time0; // microseconds
316 unsigned int nsecs = 0xf & (time0 >> 20); // nsecs * 100
317 the_time = ((double) time1) + .000001 * (double) msecs /* + .0000001 * (double) nsecs*/;
318 if (ns) {
319 *ns = 100 * nsecs; // Store nanoseconds
320 }
321 }
322 //printf("%f\n", the_time);
323 return the_time;
324 }
325
326 // Get current GPS time off the card
327 // Nanoseconds (hundreds at most) are available as an optional ns parameter
328 double getGpsTime(unsigned int *ns) {
329 return getGpsTime1(ns, 0);
330 }
331
332 // Get current EVENT time off the card
333 // Nanoseconds (hundreds at most) are available as an optional ns parameter
334 double getGpsEventTime(unsigned int *ns) {
335 return getGpsTime1(ns, 1);
336 }
337
338 // Get Gps card microseconds
339 unsigned int getGpsUsec() {
340
341 if (cdsPciModules.gps) {
342 // Sample time
343 cdsPciModules.gps[0] = 1;
344 // Read microseconds, nanoseconds
345 unsigned int time0 = cdsPciModules.gps[SYMCOM_BC635_TIME0/4];
346 unsigned int time1 = cdsPciModules.gps[SYMCOM_BC635_TIME1/4];
347 return 0xfffff & time0; // microseconds
348 }
349 return 0;
350 }
351
352 /************************************************************************/
353 /* TASK: fe_start() */
354 /* This routine is the skeleton for all front end code */
355 /************************************************************************/
356 void *fe_start(void *arg)
357 {
358
359 int ii,jj,kk;
360 static int clock1Min = 0;
361 static int cpuClock[10];
362 int adcData[MAX_ADC_MODULES][32];
363 volatile int *packedData;
364 volatile unsigned int *pDacData;
365 RFM_FE_COMMS *pEpicsComms;
366 int cycleTime;
367 int timeHold = 0;
368 int timeHoldMax = 0;
369 int myGmError2 = 0;
370 int attemptingReconnect = 0;
371 int status;
372 float onePps;
373 int onePpsHi = 0;
374 int dcuId;
375 static int adcTime;
376 static int adcHoldTime;
377 static int usrTime;
378 static int usrHoldTime;
379 int netRetry;
380 float xExc[10];
381 static int skipCycle = 0;
382 int diagWord = 0;
383 int timeDiag = 0;
384 int epicsCycle = 0;
385 int system = 0;
386
387
388 // Do all of the initalization
389
390 /* Init comms with EPICS processor */
391 pEpicsComms = (RFM_FE_COMMS *)_epics_shm;
392 pLocalEpics = (CDS_EPICS *)&pEpicsComms->epicsSpace;
393
394 #ifdef OVERSAMPLE
395 // Zero out filter histories
396 memset(dHistory, 0, sizeof(dHistory));
397 memset(dDacHistory, 0, sizeof(dDacHistory));
398 //printf("Coeff history sizes are %d %d\n", sizeof(dHistory), sizeof(dDacHistory));
399 #endif
400
401 // Zero out DAC outputs
402 for (ii = 0; ii < MAX_DAC_MODULES; ii++)
403 for (jj = 0; jj < 16; jj++) {
404 dacOut[ii][jj] = 0.0;
405 dacOutUsed[ii][jj] = 0;
406 }
407
408 // Set pointers to SFM data buffers
409 #if NUM_SYSTEMS > 1
410 for (system = 0; system < NUM_SYSTEMS; system++) {
411 pDsp[system] = (FILT_MOD *)(&pEpicsComms->dspSpace[system]);
412 pCoeff[system] = (VME_COEF *)(&pEpicsComms->coeffSpace[system]);
413 dspPtr[system] = dsp + system;
414 }
415 #else
416 pDsp[system] = (FILT_MOD *)(&pEpicsComms->dspSpace);
417 pCoeff[system] = (VME_COEF *)(&pEpicsComms->coeffSpace);
418 dspPtr[system] = dsp;
419 #endif
420
421 // Clear the FE reset which comes from Epics
422 pLocalEpics->epicsInput.vmeReset = 0;
423
424 // Do not proceed until EPICS has had a BURT restore
425 unsigned int ns;
426 double time = getGpsTime(&ns);
427 printf("Waiting for EPICS BURT at %f and %d ns\n", time, ns);
428 do{
429 usleep(1000000);
430 }while(!pLocalEpics->epicsInput.burtRestore);
431 for (system = 0; system < NUM_SYSTEMS; system++)
432 {
433 for(ii=0;ii<END_OF_DAQ_BLOCK;ii++)
434 {
435 updateEpics(ii, dspPtr[system], pDsp[system],
436 &dspCoeff[system], pCoeff[system]);
437 }
438 }
439
440 // Need this FE dcuId to make connection to FB
441 dcuId = pLocalEpics->epicsInput.dcuId;
442
443 pLocalEpics->epicsOutput.diagWord = 0;
444 pLocalEpics->epicsOutput.timeDiag = 0;
445
446
447 #ifdef PNM
448 dcuId = 9;
449 #endif
450 #ifndef NO_DAQ
451 // Make connections to FrameBuilder
452 printf("Waiting for Network connect to FB - %d\n",dcuId);
453 netRetry = 0;
454 status = cdsDaqNetReconnect(dcuId);
455 printf("Reconn status = %d %d\n",status,numFb);
456 do{
457 usleep(10000);
458 status = cdsDaqNetCheckReconnect();
459 netRetry ++;
460 }while((status < numFb) && (netRetry < 10));
461 printf("Reconn Check = %d %d\n",status,numFb);
462
463 if(fbStat[0] & 1) fbStat[0] = 3;
464 if(fbStat[1] & 1) fbStat[1] = 3;
465 #endif
466
467 /* Initialize filter banks */
468 for (system = 0; system < NUM_SYSTEMS; system++) {
469 for(ii=0;ii<MAX_MODULES;ii++){
470 for(jj=0;jj<FILTERS;jj++){
471 for(kk=0;kk<MAX_COEFFS;kk++){
472 dspCoeff[system].coeffs[ii].filtCoeff[jj][kk] = 0.0;
473 }
474 dspCoeff[system].coeffs[ii].filtSections[jj] = 0;
475 }
476 }
477 }
478
479 /* Initialize all filter module excitation signals to zero */
480 for (system = 0; system < NUM_SYSTEMS; system++)
481 for(ii=0;ii<MAX_MODULES;ii++)
482 dsp[system].data[ii].exciteInput = 0.0;
483
484
485 /* Initialize DSP filter bank values */
486 for (system = 0; system < NUM_SYSTEMS; system++)
487 if (initVars(dsp + system, pDsp[system], dspCoeff + system, MAX_MODULES, pCoeff[system])) {
488 printf("Filter module init failed, exiting\n");
489 return 0;
490 }
491
492 printf("Initialized servo control parameters.\n");
493
494
495
496
497 #ifndef NO_DAQ
498 /* Set data range limits for daqLib routine */
499 #ifdef SERVO2K
500 daq.filtExMin = 20001;
501 daq.filtTpMin = 30001;
502 #else
503 daq.filtExMin = 1;
504 daq.filtTpMin = 10001;
505 #endif
506 daq.filtExMax = daq.filtExMin + MAX_MODULES;
507 daq.filtExSize = MAX_MODULES;
508 daq.xExMin = -1;
509 daq.xExMax = -1;
510 daq.filtTpMax = daq.filtTpMin + MAX_MODULES * 3;
511 daq.filtTpSize = MAX_MODULES * 3;
512 daq.xTpMin = daq.filtTpMax;
513 daq.xTpMax = daq.xTpMin + 50;
514
515 printf("DAQ Ex Min/Max = %d %d\n",daq.filtExMin,daq.filtExMax);
516 printf("DAQ Tp Min/Max = %d %d\n",daq.filtTpMin,daq.filtTpMax);
517 printf("DAQ XTp Min/Max = %d %d\n",daq.xTpMin,daq.xTpMax);
518
519 // Set an xtra TP to read out one pps signal
520 testpoint[0] = (float *)&onePps;
521 #endif
522 pLocalEpics->epicsOutput.diags[1] = 0;
523 pLocalEpics->epicsOutput.diags[2] = 0;
524
525 #if defined(OMC_CODE) && !defined(COMPAT_INITIAL_LIGO)
526 if (cdsPciModules.pci_rfm[0] != 0) {
527 lscRfmPtr = (float *)(cdsPciModules.pci_rfm[0] + 0x3000);
528 } else {
529 lscRfmPtr = 0;
530 }
531 #endif
532
533 #ifndef NO_DAQ
534 // Initialize DAQ function
535 status = daqWrite(0,dcuId,daq,DAQ_RATE,testpoint,dspPtr[0],0,pLocalEpics->epicsOutput.gdsMon,xExc);
536 if(status == -1)
537 {
538 printf("DAQ init failed -- exiting\n");
539 vmeDone = 1;
540 #if NUM_SYSTEMS > 1
541 feDone();
542 #endif
543 return(0);
544 }
545 #endif
546 //Read Dio card initial values
547 for(kk=0;kk<cdsPciModules.doCount;kk++)
548 {
549 ii = cdsPciModules.doInstance[kk];
550 if(cdsPciModules.doType[kk] == ACS_8DIO)
551 {
552 rioInput[ii] = readIiroDio(&cdsPciModules, kk) & 0xff;
553 }
554 if(cdsPciModules.doType[kk] == ACS_16DIO)
555 {
556 rioInput1[ii] = readIiroDio1(&cdsPciModules, kk) & 0xffff;
557 }
558 if(cdsPciModules.doType[kk] == CON_32DO)
559 {
560 CDO32Input[ii] = readCDO32l(&cdsPciModules, kk);
561 }
562 }
563
564 // Clear the startup sync counter
565 firstTime = 0;
566
567 // Clear the code exit flag
568 vmeDone = 0;
569 feCode(clock16K,dWord,dacOut,dspPtr[0],&dspCoeff[0],pLocalEpics,1);
570
571 printf("entering the loop\n");
572
573 // Clear a couple of timing diags.
574 adcHoldTime = 0;
575 usrHoldTime = 0;
576
577 // Initialize the ADC/DAC DMA registers
578 for(jj=0;jj<cdsPciModules.adcCount;jj++)
579 {
580 status = gsaAdcDma1(jj,cdsPciModules.adcType[jj],ADC_DMA_BYTES);
581 packedData = (int *)cdsPciModules.pci_adc[jj];
582 *packedData = 0x0;
583 if (cdsPciModules.adcType[jj] == GSC_16AISS8AO4
584 || cdsPciModules.adcType[jj] == GSC_18AISS8AO8) {
585 packedData += 3;
586 } else packedData += 31;
587 *packedData = 0x110000;
588 }
589
590 for(jj = 0; jj < cdsPciModules.dacCount; jj++) {
591 status = gsaDacDma1(jj, cdsPciModules.dacType[jj]);
592
593 pDacData = (unsigned int *) cdsPciModules.pci_dac[jj];
594
595 // Preload DAC values
596 #ifdef DAC_OVER2
597 for(ii = 0; ii < (OVERSAMPLE_TIMES * 32); ii++) {
598 #else
599 for(ii = 0; ii < (OVERSAMPLE_TIMES * 16); ii++) {
600 #endif
601 *pDacData = 0; // (unsigned int) 10000; // for testing with the scope
602 pDacData ++;
603 }
604
605 gsaDacDma2(jj, cdsPciModules.dacType[jj]);
606 }
607
608 #ifndef NO_SYNC
609 if (run_on_timer) {
610 #endif
611 // See if GPS card present
612 cycle_gps_time = getGpsTime(&cycle_gps_ns);
613 if (cycle_gps_time != 0.0) {
614 unsigned int usec;
615 // Enable external event GPS time capture
616 cdsPciModules.gps[SYMCOM_BC635_CONTROL/4] = 8;
617
618 // Sleep a second and a half
619 usleep(1500000);
620
621 // Get the 1PPS time stamp
622 cycle_gps_event_time = getGpsEventTime(&cycle_gps_event_ns);
623 printf("Initial 1PPS time stamp is %d\n", cycle_gps_event_time);
624
625 usec = 1000000 * (cycle_gps_event_time - (unsigned int) cycle_gps_event_time);
626 if (usec > 500000) usec -= 1000000;
627 //pLocalEpics->epicsOutput.onePps = usec;
628
629 //while ((usec = getGpsUsec()) < 999978);// Wait until 22us before sec
630 printf("1PPS usec delay is %d\n", usec);
631 int delay = 10 + usec;
632 int wt = 1000000 - delay;
633 if (wt > 1000000) wt = 2000000 - wt;
634 printf("Waiting until usec = %d to start the ADCs\n", wt);
635 while ((usec = getGpsUsec()) < wt);
636
637 printf("Running time %d us\n", usec);
638 } else {
639 // Pause until this second ends
640 struct timespec next;
641 clock_gettime(CLOCK_REALTIME, &next);
642 printf("Start time %ld s %ld ns\n", next.tv_sec, next.tv_nsec);
643 next.tv_nsec = 0;
644 next.tv_sec += 1;
645 clock_nanosleep(CLOCK_REALTIME, TIMER_ABSTIME, &next, NULL);
646 clock_gettime(CLOCK_REALTIME, &next);
647 printf("Running time %ld s %ld ns\n", next.tv_sec, next.tv_nsec);
648 }
649 #ifndef NO_SYNC
650 }
651 #endif
652
653 if (!run_on_timer) {
654 // Trigger the ADC to start running
655 gsaAdcTrigger(cdsPciModules.adcCount,cdsPciModules.adcType);
656 #ifdef SERVO128K
657 gsaDacTrigger(cdsPciModules.dacCount);
658 #endif
659 #ifdef SERVO64K
660 gsaDacTrigger(cdsPciModules.dacCount);
661 #endif
662 #ifdef SERVO32K
663 gsaDacTrigger(cdsPciModules.dacCount);
664 #endif
665 #ifdef NO_SYNC
666 gsaDacTrigger(cdsPciModules.dacCount);
667 printf("Triggered the DAC\n");
668 #endif
669 } else {
670 printf("*******************************\n");
671 printf("* Running with RTLinux timer! *\n");
672 printf("*******************************\n");
673 }
674
675 printf("Triggered the ADC\n");
676 #ifdef OMC_CODE
677 cdsPciModules.gps = 0;
678 #endif
679 cdsPciModules.gps = 0;
680
681 // Total number of various binary I/O modules
682 unsigned int total_bio_boards = cdsPciModules.dioCount
683 + cdsPciModules.iiroDioCount
684 + cdsPciModules.iiroDio1Count
685 + cdsPciModules.cDo32lCount;
686 // 0 to total_bio_boards*2 counter
687 int cur_bio_card = 0; // Current binary I/O module we read or write
688
689 // Enter the coninuous FE control loop **********************************************************
690 while(!vmeDone){
691
692 rdtscl(cpuClock[2]);
693 if (run_on_timer) {
694 // Pause until next cycle begins
695 struct timespec next;
696 clock_gettime(CLOCK_REALTIME, &next);
697 if (clock16K == 0) {
698 next.tv_nsec = 0;
699 next.tv_sec += 1;
700 } else {
701 next.tv_nsec = 1000000000 / CYCLE_PER_SECOND * clock16K;
702 }
703 clock_nanosleep(CLOCK_REALTIME, TIMER_ABSTIME, &next, NULL);
704 } else {
705 // Wait for data ready from first ADC module.
706 if (cdsPciModules.adcType[0] == GSC_16AISS8AO4
707 || cdsPciModules.adcType[0] == GSC_18AISS8AO8)
708 {
709 status = checkAdcRdy(ADC_SAMPLE_COUNT,0);
710 if (status == -1) {
711 stop_working_threads = 1;
712 printf("timeout 0\n");
713 }
714 } else {
715 // ADC is running in DEMAND DMA MODE
716 packedData = (int *)cdsPciModules.pci_adc[0];
717 kk = 0;
718 do {
719 kk ++;
720 }while((*packedData == 0) && (kk < 10000000));
721 if (kk == 10000000) {
722 stop_working_threads = 1;
723 printf("timeout 0\n");
724 }
725 }
726
727 usleep(0);
728 }
729
730 #if 0
731 if ((firstTime == 200) && (clock16K == (CYCLE_PER_SECOND - 3)))
732 {
733 printf("firstTime=%d clock16K = %d\n", firstTime, clock16K);
734
735 gsaDacTrigger(cdsPciModules.dacCount);
736 firstTime = 300;
737 }
738 #endif
739 // Read CPU clock for timing info
740 rdtscl(cpuClock[0]);
741
742 // Get the time from the GPS board
743 cycle_gps_time = getGpsTime(&cycle_gps_ns);
744 cycle_gps_event_time = getGpsEventTime(&cycle_gps_event_ns);
745 // printf("%f\n", cycle_gps_time - cycle_gps_event_time);
746 timeDiag |= gps_receiver_unlocked;
747
748 if (!run_on_timer) {
749 for(jj=0;jj<cdsPciModules.adcCount;jj++) {
750 if(cdsPciModules.adcType[jj] == GSC_16AISS8AO4
751 || cdsPciModules.adcType[jj] == GSC_18AISS8AO8)
752 {
753 gsaAdcDma2(jj);
754 }
755 }
756 // Wait until all ADC channels have been updated
757 for(jj=0;jj<cdsPciModules.adcCount;jj++) {
758 packedData = (int *)cdsPciModules.pci_adc[jj];
759 if(cdsPciModules.adcType[jj] == GSC_16AISS8AO4) packedData += 3;
760 else if(cdsPciModules.adcType[jj] == GSC_18AISS8AO8) packedData += 3;
761 else packedData += 31;
762 kk = 0;
763 // This seems to work for 18-bit board, not sure this is
764 // completely correct
765 if (cdsPciModules.adcType[jj] == GSC_18AISS8AO8) {
766 do {
767 kk ++;
768 }while(((*packedData & 0x040000) > 0) && (kk < 10000000));
769 } else {
770 do {
771 kk ++;
772 }while(((*packedData & 0x110000) > 0) && (kk < 10000000));
773 }
774 if (kk == 10000000) {
775 stop_working_threads = 1;
776 rdtscl(cpuClock[5]);
777 printf("Adc %d timeout 1 %d\n", jj,((cpuClock[5] - cpuClock[2])/CPURATE));
778 }
779 }
780 }
781
782 // Update internal cycle counters
783 if((firstTime != 0) && (!skipCycle))
784 {
785 clock16K += 1;
786 clock16K %= CYCLE_PER_SECOND;
787 clock1Min += 1;
788 clock1Min %= CYCLE_PER_MINUTE;
789 if(subcycle == DAQ_CYCLE_CHANGE) daqCycle = (daqCycle + 1) % 16;
790 if(subcycle == END_OF_DAQ_BLOCK) /*we have reached the 16Hz second barrier*/
791 {
792 /* Reset the data cycle counter */
793 subcycle = 0;
794
795 }
796 else{
797 /* Increment the internal cycle counter */
798 subcycle ++;
799 }
800 }
801 if((subcycle == 0) && (daqCycle == 15))
802 {
803 pLocalEpics->epicsOutput.cpuMeter = timeHold;
804 pLocalEpics->epicsOutput.cpuMeterMax = timeHoldMax;
805 timeHold = 0;
806 pLocalEpics->epicsOutput.adcWaitTime = adcHoldTime;
807 if(adcHoldTime > CYCLE_TIME_ALRM) diagWord |= FE_ADC_HOLD_ERR;
808 if(timeHoldMax > CYCLE_TIME_ALRM) diagWord |= FE_PROC_TIME_ERR;
809 if(pLocalEpics->epicsInput.diagReset || initialDiagReset)
810 {
811 initialDiagReset = 0;
812 pLocalEpics->epicsInput.diagReset = 0;
813 adcHoldTime = 0;
814 timeHoldMax = 0;
815 printf("DIAG RESET\n");
816 }
817 pLocalEpics->epicsOutput.diagWord = diagWord;
818 diagWord = 0;
819 pLocalEpics->epicsOutput.timeDiag = timeDiag;
820 timeDiag = 0;
821 }
822
823 /* Update Epics variables */
824 #if MAX_MODULES > END_OF_DAQ_BLOCK
825 epicsCycle = (epicsCycle + 1) % (MAX_MODULES + 2);
826 #else
827 epicsCycle = subcycle;
828 #endif
829 for (system = 0; system < NUM_SYSTEMS; system++)
830 updateEpics(epicsCycle, dspPtr[system], pDsp[system],
831 &dspCoeff[system], pCoeff[system]);
832
833 vmeDone = stop_working_threads | checkEpicsReset(epicsCycle, pLocalEpics);
834 // usleep(1);
835 if (!run_on_timer) {
836 // Wait for completion of DMA of Adc data
837 for(kk=0;kk<cdsPciModules.adcCount;kk++) {
838 // Read adc data into local variables
839 packedData = (int *)cdsPciModules.pci_adc[kk];
840 // Return 0x10 if first ADC channel does not have sync bit set
841 if(*packedData & 0xf0000) status = 0;
842 else status = 16;
843 jj = kk + 1;
844 diagWord |= status * jj;
845
846 int limit = 32000;
847 int offset = 0x8000;
848 int mask = 0xffff;
849 int num_outs = 32;
850 if (cdsPciModules.adcType[kk] == GSC_18AISS8AO8) {
851 limit *= 4; // 18 bit limit
852 offset = 0x20000; // Data coding offset in 18-bit DAC
853 mask = 0x3ffff;
854 num_outs = 8;
855 }
856 if (cdsPciModules.adcType[kk] == GSC_16AISS8AO4) {
857 num_outs = 4;
858 }
859 #ifdef OVERSAMPLE
860 for (jj=0; jj < OVERSAMPLE_TIMES; jj++)
861 {
862 for(ii=0;ii<num_outs;ii++)
863 {
864 adcData[kk][ii] = (*packedData & mask);
865 adcData[kk][ii] -= offset;
866 if (ii == 31) {
867 if (jj == 0 || dWord[kk][31] < adcData[kk][31])
868 dWord[kk][31] = adcData[kk][31];
869 } else {
870 if (dWordUsed[kk][ii]) {
871 dWord[kk][ii] = iir_filter((double)adcData[kk][ii],FE_OVERSAMPLE_COEFF,2,&dHistory[ii+kk*32][0]);
872 }
873 }
874 packedData ++;
875 }
876 }
877 //dWord[kk][31] = adcData[kk][31];
878 #else
879 for(ii=0;ii<num_outs;ii++)
880 {
881 adcData[kk][ii] = (*packedData & mask);
882 adcData[kk][ii] -= offset;
883 packedData ++;
884 dWord[kk][ii] = adcData[kk][ii];
885 }
886 #endif
887 for(ii=0;ii<32;ii++)
888 {
889 if((adcData[kk][ii] > limit) || (adcData[kk][ii] < -limit))
890 {
891 overflowAdc[kk][ii] ++;
892 // pLocalEpics->epicsOutput.ovAccum ++;
893 overflowAcc ++;
894 diagWord |= 0x100 * jj;
895 }
896 }
897 // Clear out last ADC data read for test on next cycle
898 packedData = (int *)cdsPciModules.pci_adc[kk];
899 *packedData = 0x0;
900 if(cdsPciModules.adcType[kk] == GSC_16AISS8AO4) packedData += 3;
901 else if(cdsPciModules.adcType[kk] == GSC_18AISS8AO8) packedData += 3;
902 else packedData += 31;
903 *packedData = 0x110000;
904 }
905 }
906
907 // Assign chan 32 to onePps
908 onePps = dWord[0][31];
909
910 // For startup sync to 1pps, loop here
911 if(firstTime == 0)
912 {
913 if(onePps > ONE_PPS_THRESH)
914 {
915 firstTime = 100;
916 #ifdef SERVO64K
917 firstTime = 200;
918 #endif
919 onePpsHi = 0;
920 }
921 #ifdef NO_SYNC
922 firstTime = 200;
923 onePpsHi = 0;
924 #endif
925 /* Do not do 1PPS sync when running on timer */
926 if (run_on_timer) {
927 firstTime = 200;
928 onePpsHi = 0;
929 }
930 }
931
932 if((onePps > ONE_PPS_THRESH) && (onePpsHi == 0))
933 {
934 #ifdef NO_SYNC
935 unsigned int usec = 1000000 * (cycle_gps_event_time - (unsigned int) cycle_gps_event_time);
936 if (usec > 500000) usec -= 1000000;
937 pLocalEpics->epicsOutput.onePps = usec;
938 #else
939 pLocalEpics->epicsOutput.onePps = clock16K;
940 #endif
941 onePpsHi = 1;
942 }
943 if(onePps < ONE_PPS_THRESH) onePpsHi = 0;
944
945 // Display sample 0 GPS microseconds
946 if (clock16K == 0) {
947 unsigned int nsec = 1000000000.0 * (cycle_gps_time - (unsigned int) cycle_gps_time);
948 if (nsec > 500000000) nsec -= 1000000000;
949 pLocalEpics->epicsOutput.timeErr = nsec;
950 }
951
952 // Check if front end continues to be in sync with 1pps
953 // If not, set sync error flag
954 if(pLocalEpics->epicsOutput.onePps > 20) diagWord |= FE_SYNC_ERR;
955
956 if(!skipCycle)
957 {
958 // Call the front end specific software
959 rdtscl(cpuClock[4]);
960
961
962 #if (NUM_SYSTEMS > 1) && !defined(PNM)
963 for (system = 0; system < 1; system++)
964 feCode(clock16K,dWord,dacOut,dspPtr[system],dspCoeff + system,pLocalEpics, system);
965 #else
966 feCode(clock16K,dWord,dacOut,dspPtr[0],&dspCoeff[0],pLocalEpics,0);
967 #endif
968 rdtscl(cpuClock[5]);
969 // pLocalEpics->epicsOutput.diags[1] = readDio(&cdsPciModules,0);
970
971 #if defined(OMC_CODE) && !defined(COMPAT_INITIAL_LIGO)
972 if (lscRfmPtr != 0) {
973 *lscRfmPtr = dspPtr[0]->data[LSC_DRIVE].output;
974 }
975 #endif
976
977 // Write out data to DAC modules
978 if((firstTime >= 200))
979 {
980 for(jj=0;jj<cdsPciModules.dacCount;jj++)
981 {
982 // Check Dac output overflow and write to DMA buffer
983 pDacData = (unsigned int *)cdsPciModules.pci_dac[jj];
984 #ifdef OVERSAMPLE_DAC
985 #ifdef DAC_OVER2
986 for (kk=0; kk < (OVERSAMPLE_TIMES*2); kk++) {
987 #else
988 for (kk=0; kk < OVERSAMPLE_TIMES; kk++) {
989 #endif
990 #endif
991 int limit = 32000;
992 int offset = 0; //0x8000;
993 int mask = 0xffff;
994 int num_outs = 16;
995 if (cdsPciModules.dacType[jj] == GSC_18AISS8AO8) {
996 limit *= 4; // 18 bit limit
997 offset = 0x20000; // Data coding offset in 18-bit DAC
998 mask = 0x3ffff;
999 num_outs = 8;
1000 }
1001 if (cdsPciModules.dacType[jj] == GSC_16AISS8AO4) {
1002 num_outs = 4;
1003 }
1004 for (ii=0; ii < num_outs; ii++)
1005 {
1006 #ifdef OVERSAMPLE_DAC
1007 if (dacOutUsed[jj][ii]) {
1008 double dac_in = kk == 0? (double)dacOut[jj][ii]: 0.0;
1009 #ifdef DAC_OVER2
1010 dacOut[jj][ii] = iir_filter(dac_in,&feCoeff4x,2,&dDacHistory[ii+jj*16][0]);
1011 dacOut[jj][ii] *= (OVERSAMPLE_TIMES * 2);
1012 #else
1013 dacOut[jj][ii] = iir_filter(dac_in,FE_OVERSAMPLE_COEFF,2,&dDacHistory[ii+jj*16][0]);
1014 dacOut[jj][ii] *= OVERSAMPLE_TIMES;
1015 #endif
1016 }
1017 #endif
1018 if(dacOut[jj][ii] > limit)
1019 {
1020 dacOut[jj][ii] = limit;
1021 overflowDac[jj][ii] ++;
1022 // pLocalEpics->epicsOutput.ovAccum ++;
1023 overflowAcc ++;
1024 diagWord |= 0x1000 * (jj+1);
1025 }
1026 if(dacOut[jj][ii] < -limit)
1027 {
1028 dacOut[jj][ii] = -limit;
1029 overflowDac[jj][ii] ++;
1030 // pLocalEpics->epicsOutput.ovAccum ++;
1031 overflowAcc ++;
1032 diagWord |= 0x1000 * (jj+1);
1033 }
1034 int dac_out = dacOut[jj][ii];
1035 dac_out += offset;
1036 //if (ii == 0) printf("%d\n", dac_out);
1037 *pDacData = (unsigned int)(dac_out & mask);
1038 pDacData ++;
1039 }
1040 #ifdef OVERSAMPLE_DAC
1041 }
1042 #endif
1043 // DMA out dac values
1044 gsaDacDma2(jj,cdsPciModules.dacType[jj]);
1045 }
1046 }
1047
1048 // Read Dio cards once per second
1049 if((firstTime >= 200))
1050 {
1051 if(clock16K < cdsPciModules.doCount)
1052 {
1053 kk = clock16K;
1054 ii = cdsPciModules.doInstance[kk];
1055 if(cdsPciModules.doType[kk] == ACS_8DIO)
1056 {
1057 rioInput[ii] = readIiroDio(&cdsPciModules, kk) & 0xff;
1058 }
1059 if(cdsPciModules.doType[kk] == ACS_16DIO)
1060 {
1061 rioInput1[ii] = readIiroDio1(&cdsPciModules, kk) & 0xffff;
1062 // printf("read 16bit dio %d %d\n",kk,rioInput1[ii]);
1063 }
1064 }
1065 // Write Dio cards on change
1066 for(kk=0;kk < cdsPciModules.doCount;kk++)
1067 {
1068 ii = cdsPciModules.doInstance[kk];
1069 if((cdsPciModules.doType[kk] == ACS_8DIO) && (rioOutput[ii] != rioOutputHold[ii]))
1070 {
1071 writeIiroDio(&cdsPciModules, kk, rioOutput[ii]);
1072 rioOutputHold[ii] = rioOutput[ii];
1073 }
1074 if((cdsPciModules.doType[kk] == ACS_16DIO) && (rioOutput1[ii] != rioOutputHold1[ii]))
1075 {
1076 writeIiroDio1(&cdsPciModules, kk, rioOutput1[ii]);
1077 rioOutputHold1[ii] = rioOutput1[ii];
1078 // printf("write relay mod %d = %d\n",kk,rioOutput1[ii]);
1079 }
1080 if(cdsPciModules.doType[kk] == CON_32DO)
1081 {
1082 if (CDO32Input[ii] != CDO32Output[ii]) {
1083 CDO32Input[ii] = writeCDO32l(&cdsPciModules, kk, CDO32Output[ii]);
1084 }
1085 }
1086 }
1087 }
1088
1089
1090 #ifndef NO_DAQ
1091 // Write DAQ and GDS values once we are synched to 1pps
1092 if(firstTime != 0)
1093 {
1094 // Call daqLib
1095 pLocalEpics->epicsOutput.diags[3] =
1096 daqWrite(1,dcuId,daq,DAQ_RATE,testpoint,dspPtr[0],myGmError2,pLocalEpics->epicsOutput.gdsMon,xExc);
1097 // Check if any messages received and get xmit que count.
1098 status = cdsDaqNetCheckCallback();
1099 // If callbacks pending count is high, FB must not be responding.
1100 // Check FB0
1101 if(((status & 0xff) > FE_MAX_FB_QUE) && (fbStat[0] & FE_FB_ONLINE))
1102 {
1103 printf("Net fail to fb0 \n");
1104 // Set error flag
1105 attemptingReconnect = 1;
1106 // Send FB status to on net, but not online.
1107 fbStat[0] = 0x1;
1108 }
1109 // Check FB1
1110 if((((status >> 8) & 0xff) > FE_MAX_FB_QUE) && (fbStat[1] & FE_FB_ONLINE))
1111 {
1112 printf("Net fail to fb1 - recon try\n");
1113 // Set error flag
1114 attemptingReconnect = 1;
1115 // Send FB status to on net, but not online.
1116 fbStat[1] = 0x1;
1117 }
1118
1119 // Check if any FB have returned to net as indicated by reduced send que count
1120 if((attemptingReconnect) && (clock16K == 1000))
1121 {
1122 // Check FB0
1123 if(((status & 0xff) < FE_MAX_FB_QUE) && (fbStat[0] == FE_FB_AVAIL))
1124 {
1125 // Set fbStat to include recon bit needed by myri.c code
1126 fbStat[0] = 5;
1127 // Send recon message to FB
1128 status = cdsDaqNetReconnect(dcuId);
1129 // printf("Send recon command fb0\n");
1130 }
1131 // Check FB1
1132 if((((status >> 8) & 0xff) < FE_MAX_FB_QUE) && (fbStat[1] == FE_FB_AVAIL))
1133 {
1134 // Set fbStat to include recon bit needed by myri.c code
1135 fbStat[1] = 5;
1136 // Send recon message to FB
1137 status = cdsDaqNetReconnect(dcuId);
1138 // printf("Send recon command fb1\n");
1139 }
1140 }
1141 // Once per second, check if FB are back on line
1142 if((attemptingReconnect) && (clock16K == 0))
1143 {
1144 // Clear error flag
1145 attemptingReconnect = 0;
1146 if((fbStat[0] & FE_FB_AVAIL) && ((fbStat[0] & FE_FB_ONLINE) == 0))
1147 // Set error flag
1148 attemptingReconnect = 1;
1149 if((fbStat[1] & FE_FB_AVAIL) && ((fbStat[1] & FE_FB_ONLINE) == 0))
1150 // Set error flag
1151 attemptingReconnect = 1;
1152 }
1153 }
1154 #endif
1155 }
1156
1157 skipCycle = 0;
1158 usleep(1);
1159 // Reset all ADC DMA GO bits
1160 for(jj=0;jj<cdsPciModules.adcCount;jj++)
1161 {
1162 if(cdsPciModules.adcType[jj] == GSC_16AI64SSA)
1163 {
1164 gsaAdcDma2(jj);
1165 }
1166 }
1167
1168 // Measure time to complete 1 cycle
1169 rdtscl(cpuClock[1]);
1170
1171 // Compute max time of one cycle.
1172 cycleTime = (cpuClock[1] - cpuClock[0])/CPURATE;
1173 //if (clock16K < 2) printf("cycle %d time %d\n", clock16K, cycleTime);
1174 #if defined(SERVO16K) || defined(SERVO2K)
1175 if ((firstTime == 100) && (clock16K == (CYCLE_PER_SECOND - 2)))
1176 {
1177 printf("DT firstTime=%d clock16K = %d\n", firstTime, clock16K);
1178 if((DAC_START_DELAY-cycleTime) > 0)
1179 usleep((DAC_START_DELAY-cycleTime));
1180 gsaDacTrigger(cdsPciModules.dacCount);
1181 firstTime = 200;
1182 }
1183 #endif
1184 // Hold the max cycle time over the last 1 second
1185 if(cycleTime > timeHold) timeHold = cycleTime;
1186 // Hold the max cycle time since last diag reset
1187 if(cycleTime > timeHoldMax) timeHoldMax = cycleTime;
1188 adcTime = (cpuClock[0] - cpuClock[2])/CPURATE;
1189 if(adcTime > adcHoldTime) adcHoldTime = adcTime;
1190 // Calc the max time of one cycle of the user code
1191 usrTime = (cpuClock[5] - cpuClock[4])/CPURATE;
1192 if(usrTime > usrHoldTime) usrHoldTime = usrTime;
1193
1194 if((subcycle == 0) && (daqCycle == 14))
1195 {
1196 pLocalEpics->epicsOutput.diags[0] = usrHoldTime;
1197 // Create FB status word for return to EPICS
1198 #ifdef USE_GM
1199 pLocalEpics->epicsOutput.diags[2] = (fbStat[1] & 3) * 4 + (fbStat[0] & 3);
1200 #else
1201 // There is no frame builder to front-end feedback at the moment when
1202 // not using GM (using shmem), perhaps it needs to be added
1203 pLocalEpics->epicsOutput.diags[2] = 3;
1204 #endif
1205 usrHoldTime = 0;
1206 if(pLocalEpics->epicsInput.syncReset)
1207 {
1208 pLocalEpics->epicsInput.syncReset = 0;
1209 skipCycle = 1;
1210 }
1211 if((pLocalEpics->epicsInput.overflowReset) || (overflowAcc > 0x1000000))
1212 {
1213
1214 #ifdef ROLLING_OVERFLOWS
1215 if (pLocalEpics->epicsInput.overflowReset) {
1216 for (ii = 0; ii < 16; ii++) {
1217 for (jj = 0; jj < cdsPciModules.adcCount; jj++) {
1218 overflowAdc[jj][ii] = 0;
1219 overflowAdc[jj][ii + 16] = 0;
1220 }
1221
1222 for (jj = 0; jj < cdsPciModules.dacCount; jj++) {
1223 overflowDac[jj][ii] = 0;
1224 }
1225 }
1226 }
1227 #endif
1228
1229 pLocalEpics->epicsInput.overflowReset = 0;
1230 pLocalEpics->epicsOutput.ovAccum = 0;
1231 overflowAcc = 0;
1232 }
1233 }
1234 if(clock16K == 200)
1235 {
1236 pLocalEpics->epicsOutput.ovAccum = overflowAcc;
1237 for(jj=0;jj<cdsPciModules.adcCount;jj++)
1238 {
1239 for(ii=0;ii<32;ii++)
1240 {
1241 pLocalEpics->epicsOutput.overflowAdc[jj][ii] = overflowAdc[jj][ii];
1242
1243 #ifdef ROLLING_OVERFLOWS
1244 if (overflowAdc[jj][ii] > 0x1000000) {
1245 overflowAdc[jj][ii] = 0;
1246 }
1247 #else
1248 overflowAdc[jj][ii] = 0;
1249 #endif
1250
1251 }
1252 }
1253 for(jj=0;jj<cdsPciModules.dacCount;jj++)
1254 {
1255 for(ii=0;ii<16;ii++)
1256 {
1257 pLocalEpics->epicsOutput.overflowDac[jj][ii] = overflowDac[jj][ii];
1258
1259 #ifdef ROLLING_OVERFLOWS
1260 if (overflowDac[jj][ii] > 0x1000000) {
1261 overflowDac[jj][ii] = 0;
1262 }
1263 #else
1264 overflowDac[jj][ii] = 0;
1265 #endif
1266
1267 }
1268 }
1269 }
1270
1271 }
1272
1273 #if (NUM_SYSTEMS > 1) && !defined(PNM)
1274 feDone();
1275 #endif
1276
1277 /* System reset command received */
1278 return (void *)-1;
1279 }
1280
1281 int main(int argc, char **argv)
1282 {
1283 pthread_attr_t attr;
1284 int status;
1285 int ii,jj;
1286 char fname[128];
1287
1288 jj = 0;
1289 printf("cpu clock %ld\n",cpu_khz);
1290
1291 /*
1292 * Create the shared memory area. By passing a non-zero value
1293 * for the mode, this means we also create a node in the GPOS.
1294 */
1295
1296 /* See if we can open new-style shared memory file */
1297 sprintf(fname, "/rtl_mem_%s", SYSTEM_NAME_STRING_LOWER);
1298 wfd = shm_open(fname, RTL_O_RDWR, 0666);
1299 if (wfd == -1) {
1300 //printf("Warning, couldn't open `%s' read/write (errno=%d)\n", fname, errno);
1301 wfd = shm_open("/rtl_epics", RTL_O_RDWR, 0666);
1302 if (wfd == -1) {
1303 printf("open failed for write on /rtl_epics (%d)\n",errno);
1304 rtl_perror("shm_open()");
1305 return -1;
1306 }
1307 }
1308
1309 _epics_shm = (unsigned char *)rtl_mmap(NULL,MMAP_SIZE,PROT_READ|PROT_WRITE,MAP_SHARED,wfd,0);
1310 if (_epics_shm == MAP_FAILED) {
1311 printf("mmap failed for epics shared memory area\n");
1312 rtl_perror("mmap()");
1313 return -1;
1314 }
1315
1316 // See if IPC area is available, open and map it
1317 strcpy(fname, "/rtl_mem_ipc");
1318 ipc_fd = shm_open(fname, RTL_O_RDWR, 0666);
1319 if (ipc_fd == -1) {
1320 //printf("Warning, couldn't open `%s' read/write (errno=%d)\n", fname, errno);
1321 } else {
1322 _ipc_shm = (unsigned char *)rtl_mmap(NULL,MMAP_SIZE,PROT_READ|PROT_WRITE,MAP_SHARED,ipc_fd,0);
1323 if (_ipc_shm == MAP_FAILED) {
1324 printf("mmap failed for IPC shared memory area\n");
1325 rtl_perror("mmap()");
1326 return -1;
1327 }
1328 }
1329
1330 #if defined(SHMEM_DAQ)
1331 // See if frame builder DAQ comm area available
1332 sprintf(fname, "/rtl_mem_%s_daq", SYSTEM_NAME_STRING_LOWER);
1333 daq_fd = shm_open(fname, RTL_O_RDWR, 0666);
1334 if (daq_fd == -1) {
1335 printf("Error: couldn't open `%s' read/write (errno=%d)\n", fname, errno);
1336 return -1;
1337 } else {
1338 _daq_shm = (unsigned char *)rtl_mmap(NULL,MMAP_SIZE,PROT_READ|PROT_WRITE,MAP_SHARED,daq_fd,0);
1339 if (_daq_shm == MAP_FAILED) {
1340 printf("mmap failed for DAQ shared memory area\n");
1341 rtl_perror("mmap()");
1342 return -1;
1343 }
1344 }
1345 #endif
1346
1347 {
1348 int cards = sizeof(cards_used)/sizeof(cards_used[0]);
1349
1350 printf("configured to use %d cards\n", cards);
1351 cdsPciModules.cards = cards;
1352 cdsPciModules.cards_used = cards_used;
1353 //return -1;
1354 }
1355 printf("Initializing PCI Modules\n");
1356 status = mapPciModules(&cdsPciModules);
1357 printf("%d PCI cards found\n",status);
1358 #ifdef ONE_ADC
1359 cdsPciModules.adcCount = cdsPciModules.dacCount = 1;
1360 #endif
1361 #ifdef DAC_COUNT
1362 cdsPciModules.dacCount = DAC_COUNT;
1363 #endif
1364 printf("***************************************************************************\n");
1365 printf("%d ADC cards found\n",cdsPciModules.adcCount);
1366 for(ii=0;ii<cdsPciModules.adcCount;ii++)
1367 {
1368 if(cdsPciModules.adcType[ii] == GSC_18AISS8AO8)
1369 {
1370 printf("\tADC %d is a GSC_18AISS8AO8 module\n",ii);
1371 if((cdsPciModules.adcConfig[ii] & 0x10000) > 0) jj = 4;
1372 else jj = 8;
1373 printf("\t\tChannels = %d \n",jj);
1374 printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.adcConfig[ii] & 0xfff));
1375 }
1376 if(cdsPciModules.adcType[ii] == GSC_16AISS8AO4)
1377 {
1378 printf("\tADC %d is a GSC_16AISS8AO4 module\n",ii);
1379 if((cdsPciModules.adcConfig[ii] & 0x10000) > 0) jj = 4;
1380 else jj = 8;
1381 printf("\t\tChannels = %d \n",jj);
1382 printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.adcConfig[ii] & 0xfff));
1383 }
1384 if(cdsPciModules.adcType[ii] == GSC_16AI64SSA)
1385 {
1386 printf("\tADC %d is a GSC_16AI64SSA module\n",ii);
1387 if((cdsPciModules.adcConfig[ii] & 0x10000) > 0) jj = 32;
1388 else jj = 64;
1389 printf("\t\tChannels = %d \n",jj);
1390 printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.adcConfig[ii] & 0xfff));
1391 }
1392 }
1393 printf("***************************************************************************\n");
1394 printf("%d DAC cards found\n",cdsPciModules.dacCount);
1395 for(ii=0;ii<cdsPciModules.dacCount;ii++)
1396 {
1397 if(cdsPciModules.dacType[ii] == GSC_18AISS8AO8)
1398 {
1399 printf("\tDAC %d is a GSC_18AISS8AO8 module\n",ii);
1400 if((cdsPciModules.dacConfig[ii] & 0x20000) > 0) jj = 0;
1401 else jj = 4;
1402 printf("\t\tChannels = %d \n",jj);
1403 printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.dacConfig[ii] & 0xfff));
1404 }
1405 if(cdsPciModules.dacType[ii] == GSC_16AISS8AO4)
1406 {
1407 printf("\tDAC %d is a GSC_16AISS8AO4 module\n",ii);
1408 if((cdsPciModules.dacConfig[ii] & 0x20000) > 0) jj = 0;
1409 else jj = 4;
1410 printf("\t\tChannels = %d \n",jj);
1411 printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.dacConfig[ii] & 0xfff));
1412 }
1413 if(cdsPciModules.dacType[ii] == GSC_16AO16)
1414 {
1415 printf("\tDAC %d is a GSC_16AO16 module\n",ii);
1416 if((cdsPciModules.dacConfig[ii] & 0x10000) == 0x10000) jj = 8;
1417 if((cdsPciModules.dacConfig[ii] & 0x20000) == 0x20000) jj = 12;
1418 if((cdsPciModules.dacConfig[ii] & 0x30000) == 0x30000) jj = 16;
1419 printf("\t\tChannels = %d \n",jj);
1420 if((cdsPciModules.dacConfig[ii] & 0xC0000) == 0x0000)
1421 {
1422 printf("\t\tFilters = None\n");
1423 }
1424 if((cdsPciModules.dacConfig[ii] & 0xC0000) == 0x40000)
1425 {
1426 printf("\t\tFilters = 10kHz\n");
1427 }
1428 if((cdsPciModules.dacConfig[ii] & 0xC0000) == 0x80000)
1429 {
1430 printf("\t\tFilters = 100kHz\n");
1431 }
1432 if((cdsPciModules.dacConfig[ii] & 0x100000) == 0x100000)
1433 {
1434 printf("\t\tOutput Type = Differential\n");
1435 }
1436 printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.dacConfig[ii] & 0xfff));
1437 }
1438 }
1439 printf("***************************************************************************\n");
1440 printf("%d DIO cards found\n",cdsPciModules.dioCount);
1441 printf("***************************************************************************\n");
1442 printf("%d IIRO-8 Isolated DIO cards found\n",cdsPciModules.iiroDioCount);
1443 printf("***************************************************************************\n");
1444 printf("%d IIRO-16 Isolated DIO cards found\n",cdsPciModules.iiroDio1Count);
1445 printf("***************************************************************************\n");
1446 printf("%d Contec 32ch PCIe DO cards found\n",cdsPciModules.cDo32lCount);
1447 printf("%d DO cards found\n",cdsPciModules.doCount);
1448 printf("***************************************************************************\n");
1449 printf("%d RFM cards found\n",cdsPciModules.rfmCount);
1450 for(ii=0;ii<cdsPciModules.rfmCount;ii++)
1451 {
1452 printf("\tRFM %d is a VMIC_%x module with Node ID %d\n", ii, cdsPciModules.rfmType[ii], cdsPciModules.rfmConfig[ii]);
1453 }
1454 printf("***************************************************************************\n");
1455
1456 //cdsPciModules.adcCount = 0;
1457 //cdsPciModules.dacCount = 0;
1458
1459 if (cdsPciModules.adcCount == 0 && cdsPciModules.dacCount == 0) {
1460 printf("No ADC and no DAC modules found, running on timer\n");
1461 run_on_timer = 1;
1462 //munmap(_epics_shm, MMAP_SIZE);
1463 //close(wfd);
1464 //return 0;
1465 }
1466 #ifdef ONE_ADC
1467 cdsPciModules.adcCount = 1;
1468 #endif
1469
1470 printf("Initializing space for daqLib buffers\n");
1471 daqBuffer = (long)&daqArea[0];
1472
1473 #ifndef NO_DAQ
1474 printf("Initializing Network\n");
1475 numFb = cdsDaqNetInit(2);
1476 if (numFb <= 0) {
1477 printf("Couldn't initialize Myrinet network connection\n");
1478 return 0;
1479 }
1480 printf("Found %d frameBuilders on network\n",numFb);
1481 #endif
1482 #if 0
1483 /* initialize the semaphore */
1484 sem_init (&irqsem, 1, 0);
1485 #endif
1486
1487
1488
1489 rtl_pthread_attr_init(&attr);
1490 #ifdef RESERVE_CPU2
1491 rtl_pthread_attr_setcpu_np(&attr, 2);
1492 rtl_pthread_attr_setreserve_np(&attr, 1);
1493 rtl_pthread_create(&wthread1, &attr, cpu2_start, 0);
1494 printf("Started cpu2 task\n");
1495 usleep(1000000);
1496 #endif
1497
1498 #ifdef RESERVE_CPU3
1499 rtl_pthread_attr_setcpu_np(&attr, 3);
1500 rtl_pthread_attr_setreserve_np(&attr, 1);
1501 rtl_pthread_create(&wthread2, &attr, cpu3_start, 0);
1502 printf("Started cpu3 task\n");
1503 usleep(1000000);
1504 #endif
1505
1506 #ifdef SPECIFIC_CPU
1507 rtl_pthread_attr_setcpu_np(&attr, SPECIFIC_CPU);
1508 #else
1509 rtl_pthread_attr_setcpu_np(&attr, 1);
1510 #endif
1511 /* mark this CPU as reserved - only RTLinux runs on it */
1512 rtl_pthread_attr_setreserve_np(&attr, 1);
1513 rtl_pthread_create(&wthread, &attr, fe_start, 0);
1514
1515
1516 #if 0
1517 /* install a handler for this IRQ */
1518 if ( (ret = rtl_request_irq( 24, intr_handler )) != 0 ) {
1519 printf("failed to get irq %d\n", 40);
1520 ret = -1;
1521 goto out;
1522 }
1523 #endif
1524
1525
1526 /* wait for us to be removed or killed */
1527 rtl_main_wait();
1528
1529 /* free this IRQ */
1530 #if 0
1531 rtl_free_irq(40);
1532 out:
1533 #endif
1534
1535 #ifndef NO_DAQ
1536 status = cdsDaqNetClose();
1537 #endif
1538
1539 printf("Killing work threads\n");
1540 stop_working_threads = 1;
1541
1542 /* kill the threads */
1543 rtl_pthread_cancel(wthread);
1544 rtl_pthread_join(wthread, NULL);
1545
1546 #ifdef RESERVE_CPU2
1547 rtl_pthread_cancel(wthread1);
1548 rtl_pthread_join(wthread1, NULL);
1549 #endif
1550 #ifdef RESERVE_CPU3
1551 rtl_pthread_cancel(wthread2);
1552 rtl_pthread_join(wthread2, NULL);
1553 #endif
1554
1555 /* unmap the shared memory areas */
1556 munmap(_epics_shm, MMAP_SIZE);
1557
1558 /* Note that this is a shared area created with shm_open() - we close
1559 * it with close(), but use shm_unlink() to actually destroy the area
1560 */
1561 close(wfd);
1562
1563 return 0;
1564 }
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