## page was renamed from CLIO/Plans/DigitalControl/FirstStage
## page was renamed from CLIO/digital/FirstStage
= Block diagram for First and Second Stage =

== Related tasks ==
 *P-arm signal 置き換え
 *long term measurement
  *power
  *temperature at vertex
  *humidity at vertex
  *dust at vertex

== CLIO digital block diagram: 1st stage for length signal ==
{{attachment:length.png}}

== channel number ==
=== ADC 16kHz ===
 *MC REFL:  (DC) = 1ch
 *MC Trans: 1ch
 *MC_F :1ch
 *LSC: (DC, RF) x2 = 4ch
  *Total 7ch

=== ADC 2kHz ===
  *Total 0ch

=== ADC 256Hz ===
 *Laser power 1
 *Seismic 1
 *Acoustic 1
 *Temperature 1ch
  *Total 4ch

=== DAC ===
 *MC: 1 SUS x 4 coils = 4ch
 *IFO: 1 SUS x 4 coils = 4ch
  *Total 8ch
  *(Vertex 4ch, X end 0ch, Y end 4ch)

=== Binary I/O ===
 *2SUS x 4coils = 8ch
 *MC fast gain, swirch, boost, test
 *Y arm gain, swirch, boost, test