Diff for "KAGRA/Subgroups/DGS/Circuits/AntiAliasImage"

Differences between revisions 1 and 12 (spanning 11 versions)

Anti Alias/Image

Overview

ADC/DACへの入出力のフィルターとしてAnti Alias/Imageを各チャンネルに装備する。
ADCは32ch/board、DACは16ch/board。
基本的にはLIGOの回路図をコピーか?
それに加えて、タイミング信号を入れることを考えなくてはならない。

Equipements

Rev. 1

LIGO-D070081: AdL AA and AI Filter Board
LIGO-D1000217: Chassis Power Regulator PCB
JGW-D1100583: AA Chassis Front panel
JGW-D1100584: AA Chassis Back panel
JGW-D1100585: AA and AI Chassis bottom and side panels

DSUB-LEMO adapter chassis

JGW-D1200869: DSubLemo Interface
JGW-D1200883: KAGRA DSub-Lemo Chassis top assembly
JGW-D1200880: KAGRA DSub-Lemo Interface Chassis front panel
JGW-D1200881: KAGRA DSub-Lemo Chassis rear panel
JGW-D1200882: KAGRA DSub-Lemo Chassis bottom/side panel

Reference

Common

LIGO-D070081: AdL AA and AI Filter Board
LIGO-D1000217: Chassis Power Regulator PCB

AA

LIGO-D0902783: aLIGO Anti-Alias Chassis Top Assembly Drawing
- It can be assembled like LIGO-D0902783 as DB9 and DB25 version.
LIGO-D0902782: aLIGO Anti-Alias Chassis Front Panel
LIGO-D0902784: aLIGO Anti-Alias Chassis Back Panel
LIGO-D1000673: aLIGO x10 Anti-Alias Chassis Test Plan
LIGO-D070100: ADC AA Interface

AI

LIGO-D1000305: aLIGO Anti-Image Chassis Top Assembly Drawing
LIGO-D1000551: aLIGO 18-bit DAC to Anti-Image Interface Board

ADC adapter

LIGO-D0902006: AdL General Standards 16 Bit ADC Adapter Board

DAC adapter

LIGO-D0902496: AdL General Standards 16 Bit DAC Adapter Board

KAGRA/Subgroups/DGS/Circuits/AntiAliasImage (last edited 2014-05-23 15:33:17 by OsamuMiyakawa)

-  ⇤ ← Revision 1 as of 2011-03-28 14:22:39 → 
  Size: 768
  Editor: OsamuMiyakawa
  Comment:
+   ← Revision 12 as of 2012-03-29 11:37:15 → ⇥
  Size: 3334
  Editor: OsamuMiyakawa
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 3:
+=== Overview ===
 * ADC/DACへの入出力のフィルターとしてAnti Alias/Imageを各チャンネルに装備する。
 * ADCは32ch/board、DACは16ch/board。
 * 基本的にはLIGOの回路図をコピーか?
 * それに加えて、タイミング信号を入れることを考えなくてはならない。

=== Equipements ===


==== Rev. 1 ====
 * [[https://dcc.ligo.org/cgi-bin/DocDB/ShowDocument?docid=4850|LIGO-D070081]]: AdL AA and AI Filter Board
 * [[https://dcc.ligo.org/cgi-bin/DocDB/ShowDocument?docid=8954|LIGO-D1000217]]: Chassis Power Regulator PCB
 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/DocDB/ShowDocument?docid=583|JGW-D1100583]]: AA Chassis Front panel
 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/DocDB/ShowDocument?docid=584|JGW-D1100584]]: AA Chassis Back panel
 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/DocDB/ShowDocument?docid=585|JGW-D1100585]]: AA and AI Chassis bottom and side panels

== DSUB-LEMO adapter chassis ==

 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/private/DocDB/ShowDocument?docid=869|JGW-D1200869]]: DSubLemo Interface
 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/private/DocDB/ShowDocument?docid=883|JGW-D1200883]]: KAGRA DSub-Lemo Chassis top assembly
 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/private/DocDB/ShowDocument?docid=880|JGW-D1200880]]: KAGRA DSub-Lemo Interface Chassis front panel
 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/private/DocDB/ShowDocument?docid=881|JGW-D1200881]]: KAGRA DSub-Lemo Chassis rear panel
 * [[http://gwdoc.icrr.u-tokyo.ac.jp/cgi-bin/private/DocDB/ShowDocument?docid=882|JGW-D1200882]]: KAGRA DSub-Lemo Chassis bottom/side panel

----
-Line 5:
+Line 30:
+==== Common ====
-Line 6:
+Line 32:
+ * [[https://dcc.ligo.org/cgi-bin/DocDB/ShowDocument?docid=8954|LIGO-D1000217]]: Chassis Power Regulator PCB

==== AA ====
-Line 8:
+Line 37:
- * [[https://dcc.ligo.org/cgi-bin/DocDB/ShowDocument?docid=8954|LIGO-D1000217]]: Chassis Power Regulator PCB
+ * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=7715|LIGO-D0902782]]: aLIGO Anti-Alias Chassis Front Panel
 * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=7720|LIGO-D0902784]]: aLIGO Anti-Alias Chassis Back Panel
 * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=25230|LIGO-D1000673]]: aLIGO x10 Anti-Alias Chassis Test Plan
-Line 10:
+Line 41:
- * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=25230|LIGO-D1000673]]: aLIGO x10 Anti-Alias Chassis Test Plan
+==== AI ====
 * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=9234|LIGO-D1000305]]: aLIGO Anti-Image Chassis Top Assembly Drawing
 * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=9899|LIGO-D1000551]]: aLIGO 18-bit DAC to Anti-Image Interface Board

==== ADC adapter ====
 * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=5190|LIGO-D0902006]]: AdL General Standards 16 Bit ADC Adapter Board


==== DAC adapter ====
 * [[https://dcc.ligo.org/cgi-bin/private/DocDB/ShowDocument?docid=6787|LIGO-D0902496]]: AdL General Standards 16 Bit DAC Adapter Board