Attachment 'controller.c'

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   1 /*----------------------------------------------------------------------*/
   2 /*                                                                      */
   3 /*                      -------------------                             */
   4 /*                                                                      */
   5 /*                             LIGO                                     */
   6 /*                                                                      */
   7 /*        THE LASER INTERFEROMETER GRAVITATIONAL WAVE OBSERVATORY.      */
   8 /*                                                                      */
   9 /*                     (C) The LIGO Project, 2005.                      */
  10 /*                                                                      */
  11 /*                                                                      */
  12 /*                                                                      */
  13 /* California Institute of Technology                                   */
  14 /* LIGO Project MS 18-34                                                */
  15 /* Pasadena CA 91125                                                    */
  16 /*                                                                      */
  17 /* Massachusetts Institute of Technology                                */
  18 /* LIGO Project MS 20B-145                                              */
  19 /* Cambridge MA 01239                                                   */
  20 /*                                                                      */
  21 /*----------------------------------------------------------------------*/
  22 
  23 
  24 #include "feSelectHeader.h"
  25 
  26 #ifdef NO_RTL
  27 #include <linux/version.h>
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/proc_fs.h>
  31 #include <linux/kthread.h>
  32 #include <asm/delay.h>
  33 
  34 #else
  35 #include <rtl_time.h>
  36 #include <time.h>
  37 #include <fcntl.h>
  38 #include <pthread.h>
  39 #include <unistd.h>
  40 #include <sys/mman.h>
  41 #include <stdio.h>
  42 #include <stdlib.h>
  43 #include <semaphore.h>
  44 #include <string.h>
  45 #endif
  46 #include <linux/slab.h>
  47 #include <drv/cdsHardware.h>
  48 #include "inlineMath.h"
  49 
  50 #if MX_KERNEL == 1
  51 #include <myriexpress.h>
  52 #endif
  53 #ifdef NO_RTL
  54 #include </usr/src/linux/arch/x86/include/asm/processor.h>
  55 #include </usr/src/linux/arch/x86/include/asm/cacheflush.h>
  56 #endif
  57 
  58 char *build_date = __DATE__ " " __TIME__;
  59 
  60 #ifndef NO_RTL
  61 int iop_rfm_valid = 1;
  62 #else
  63 extern int iop_rfm_valid;
  64 #endif
  65 
  66 #ifndef NUM_SYSTEMS
  67 #define NUM_SYSTEMS 1
  68 #endif
  69 
  70 #define INLINE  inline
  71 #define FE_DIAGS_USER_TIME	0
  72 #define FE_DIAGS_IPC_STAT	1
  73 #define FE_DIAGS_FB_NET_STAT	2
  74 #define FE_DIAGS_DAQ_BYTE_CNT	3
  75 #define FE_DIAGS_DUOTONE_TIME	4
  76 #define FE_DIAGS_IRIGB_TIME	5
  77 #define FE_DIAGS_ADC_STAT	6
  78 #define FE_DIAGS_DAC_STAT	7
  79 #define FE_DIAGS_DAC_MASTER_STAT	8
  80 #define FE_DIAGS_AWGTPMAN	9
  81 
  82 #define MMAP_SIZE (64*1024*1024 - 5000)
  83 volatile char *_epics_shm;		// Ptr to EPICS shared memory
  84 char *_ipc_shm;			// Ptr to inter-process communication area 
  85 #if defined(SHMEM_DAQ)
  86 char *_daq_shm;			// Ptr to frame builder comm shared mem area 
  87 int daq_fd;			// File descriptor to share memory file 
  88 #endif
  89 
  90 long daqBuffer;			// Address for daq dual buffers in daqLib.c
  91 #ifndef NO_RTL
  92 sem_t irqsem;			// Semaphore if in IRQ mode.
  93 #endif
  94 CDS_HARDWARE cdsPciModules;	// Structure of PCI hardware addresses
  95 volatile IO_MEM_DATA *ioMemData;
  96 volatile int vmeDone = 0;	// Code kill command
  97 volatile int stop_working_threads = 0;
  98 
  99 #ifdef NO_RTL
 100 #define STACK_SIZE    40000
 101 #define TICK_PERIOD   100000
 102 #define PERIOD_COUNT  1
 103 
 104 #else
 105 #include "msr.h"
 106 #endif
 107 
 108 #ifdef NO_RTL
 109 #undef NO_CPU_SHUTDOWN 1
 110 #ifndef NO_CPU_SHUTDOWN
 111 char fmt1[512];
 112 int printk(const char *fmt, ...) {
 113     va_list args;
 114     int r;
 115 
 116     strcat(strcpy(fmt1, SYSTEM_NAME_STRING_LOWER), ": ");
 117     strcat(fmt1, fmt);
 118     va_start(args, fmt1);
 119     r = vprintkl(fmt1, args);
 120     va_end(args);
 121     return r;
 122 }
 123 #endif
 124 #define printf printk
 125 #endif
 126 
 127 #ifdef DOLPHIN_TEST
 128 #include "dolphin.c"
 129 #endif
 130 
 131 #include "fm10Gen.h"		// CDS filter module defs and C code
 132 #include "feComms.h"		// Lvea control RFM network defs.
 133 #include "daqmap.h"		// DAQ network layout
 134 extern unsigned int cpu_khz;
 135 #define CPURATE	(cpu_khz/1000)
 136 #define ONE_PPS_THRESH 2000
 137 #define SYNC_SRC_NONE		0
 138 #define SYNC_SRC_IRIG_B		1
 139 #define SYNC_SRC_1PPS		2
 140 #define SYNC_SRC_TDS		4
 141 #define SYNC_SRC_MASTER		8
 142 #define TIME_ERR_IRIGB		0x10
 143 #define TIME_ERR_1PPS		0x20
 144 #define TIME_ERR_TDS		0x40
 145 
 146 #ifndef NO_DAQ
 147 #include "drv/gmnet.h"
 148 #include "drv/fb.h"
 149 #include "drv/myri.h"		// Myricom network defs
 150 #include "drv/daqLib.c"		// DAQ/GDS connection software
 151 #endif
 152 #include "drv/map.h"		// PCI hardware defs
 153 #include "drv/epicsXfer.c"	// User defined EPICS to/from FE data transfer function
 154 
 155 // Define standard values based on code rep rate **************************************
 156 #ifdef SERVO256K
 157         #define CYCLE_PER_SECOND        (2*131072)
 158         #define CYCLE_PER_MINUTE        (2*7864320)
 159         #define DAQ_CYCLE_CHANGE        (2*8000)
 160         #define END_OF_DAQ_BLOCK        (2*8191)
 161         #define DAQ_RATE                (2*8192)
 162         #define NET_SEND_WAIT           (2*655360)
 163         #define CYCLE_TIME_ALRM         4
 164 #endif
 165 #ifdef SERVO128K
 166         #define CYCLE_PER_SECOND        131072
 167         #define CYCLE_PER_MINUTE        7864320
 168         #define DAQ_CYCLE_CHANGE        8000
 169         #define END_OF_DAQ_BLOCK        8191
 170         #define DAQ_RATE                8192
 171         #define NET_SEND_WAIT           655360
 172         #define CYCLE_TIME_ALRM         7
 173 #endif
 174 #ifdef SERVO64K
 175 	#define CYCLE_PER_SECOND	(2*32768)
 176 	#define CYCLE_PER_MINUTE	(2*1966080)
 177 	#define DAQ_CYCLE_CHANGE	(2*1540)
 178 	#define END_OF_DAQ_BLOCK	4095
 179 	#define DAQ_RATE	(DAQ_16K_SAMPLE_SIZE*4)
 180 	#define NET_SEND_WAIT		(2*81920)
 181 	#define CYCLE_TIME_ALRM		15
 182 	#define CYCLE_TIME_ALRM_HI	25
 183 	#define CYCLE_TIME_ALRM_LO	10
 184 #ifdef ADC_SLAVE
 185 	#define DAC_PRELOAD_CNT		1
 186 #else
 187 	#define DAC_PRELOAD_CNT		0
 188 #endif
 189 #endif
 190 #ifdef SERVO32K
 191 	#define CYCLE_PER_SECOND	32768
 192 	#define CYCLE_PER_MINUTE	1966080
 193 	#define DAQ_CYCLE_CHANGE	1540
 194 	#define END_OF_DAQ_BLOCK	2047
 195 	#define DAQ_RATE	(DAQ_16K_SAMPLE_SIZE*2)
 196 	#define NET_SEND_WAIT		(2*81920)
 197 	#define CYCLE_TIME_ALRM_HI	38
 198 	#define CYCLE_TIME_ALRM_LO	25
 199         #define CYCLE_TIME_ALRM         31
 200 #ifdef ADC_SLAVE
 201 	#define DAC_PRELOAD_CNT		2
 202 #else
 203 	#define DAC_PRELOAD_CNT		1
 204 #endif
 205 #endif
 206 
 207 #ifdef SERVO16K
 208 	#define CYCLE_PER_SECOND	16384
 209 	#define CYCLE_PER_MINUTE	983040
 210 	#define DAQ_CYCLE_CHANGE	770
 211 	#define END_OF_DAQ_BLOCK	1023
 212 	#define DAQ_RATE	DAQ_16K_SAMPLE_SIZE
 213 	#define NET_SEND_WAIT		81920
 214 	#define CYCLE_TIME_ALRM_HI	70
 215 	#define CYCLE_TIME_ALRM_LO	50
 216         #define CYCLE_TIME_ALRM         62
 217 	#define DAC_PRELOAD_CNT		4
 218 #endif
 219 #ifdef SERVO4K
 220         #define CYCLE_PER_SECOND        4096
 221         #define CYCLE_PER_MINUTE        2*122880
 222         #define DAQ_CYCLE_CHANGE        240
 223         #define END_OF_DAQ_BLOCK        255
 224         #define DAQ_RATE        2*DAQ_2K_SAMPLE_SIZE
 225         #define NET_SEND_WAIT           2*10240
 226         #define CYCLE_TIME_ALRM         487/2
 227         #define CYCLE_TIME_ALRM_HI      500/2
 228         #define CYCLE_TIME_ALRM_LO      460/2
 229         #define DAC_PRELOAD_CNT         16      
 230 #endif
 231 #ifdef SERVO2K
 232 	#define CYCLE_PER_SECOND	2048
 233 	#define CYCLE_PER_MINUTE	122880
 234 	#define DAQ_CYCLE_CHANGE	120
 235 	#define END_OF_DAQ_BLOCK	127
 236 	#define DAQ_RATE	DAQ_2K_SAMPLE_SIZE
 237 	#define NET_SEND_WAIT		10240
 238 	#define CYCLE_TIME_ALRM		487
 239 	#define CYCLE_TIME_ALRM_HI	500
 240 	#define CYCLE_TIME_ALRM_LO	460
 241 	#define DAC_PRELOAD_CNT		8	
 242 #endif
 243 #include "drv/inputFilterModule.h"		
 244 #include "drv/inputFilterModule1.h"		
 245 
 246 #ifndef NO_DAQ
 247 DAQ_RANGE daq;			// Range settings for daqLib.c
 248 int numFb = 0;
 249 int fbStat[2] = {0,0};		// Status of DAQ backend computer
 250 #endif
 251 
 252 #ifdef NO_RTL
 253 ;
 254 #else
 255 rtl_pthread_t wthread;
 256 rtl_pthread_t wthread1;
 257 rtl_pthread_t wthread2;
 258 #endif
 259 int wfd, ipc_fd;
 260 
 261 /* ADC/DAC overflow variables */
 262 int overflowAdc[MAX_ADC_MODULES][32];;
 263 int overflowDac[MAX_DAC_MODULES][16];;
 264 int overflowAcc = 0;
 265 
 266 float *testpoint[500];	// Testpoints which are not part of filter modules
 267 float xExc[50];	// GDS EXC not associated with filter modules
 268 float floatDacOut[160]; // DAC outputs stored as floats, to be picked up as test points
 269 
 270 volatile CDS_EPICS *pLocalEpics;   	// Local mem ptr to EPICS control data
 271 
 272 
 273 // 1/16 sec cycle counters for DAQS and ISC RFM IPC
 274 int subcycle = 0;		// Internal cycle counter	 
 275 unsigned int daqCycle;		// DAQS cycle counter	
 276 
 277 
 278 FILT_MOD dsp[NUM_SYSTEMS];			// SFM structure.	
 279 FILT_MOD *dspPtr[NUM_SYSTEMS];			// SFM structure pointer.
 280 FILT_MOD *pDsp[NUM_SYSTEMS];			// Ptr to SFM in shmem.	
 281 COEF dspCoeff[NUM_SYSTEMS];			// Local mem for SFM coeffs.
 282 VME_COEF *pCoeff[NUM_SYSTEMS];			// Ptr to SFM coeffs in shmem	
 283 double dWord[MAX_ADC_MODULES][32];		// ADC read values
 284 unsigned int dWordUsed[MAX_ADC_MODULES][32];	// ADC chans used by app code
 285 double dacOut[MAX_DAC_MODULES][16];		// DAC output values
 286 int dacOutEpics[MAX_DAC_MODULES][16];		// DAC outputs reported back to EPICS
 287 unsigned int dacOutUsed[MAX_DAC_MODULES][16];	// DAC chans used by app code
 288 int dioInput[MAX_DIO_MODULES];			// BIO card inputs
 289 int dioOutput[MAX_DIO_MODULES];			// BIO card outputs
 290 int dioOutputHold[MAX_DIO_MODULES];			// BIO card outputs
 291 
 292 // Relay digital I/O cards read operations
 293 // 0 - do not read card registers
 294 // 1 - read digital inputs
 295 // 2 - read digital outputs
 296 // 3 - both
 297 int rioReadOps[MAX_DIO_MODULES];
 298 // Values read from relay digital I/O cards, current input values
 299 int rioInputInput[MAX_DIO_MODULES];
 300 // Values read from relay digital I/O cards, current output values
 301 int rioInputOutput[MAX_DIO_MODULES];
 302 
 303 int rioOutput[MAX_DIO_MODULES];
 304 int rioOutputHold[MAX_DIO_MODULES];
 305 int rioInput1[MAX_DIO_MODULES];
 306 int rioOutput1[MAX_DIO_MODULES];
 307 int rioOutputHold1[MAX_DIO_MODULES];
 308 unsigned int CDO32Input[MAX_DIO_MODULES];
 309 unsigned int CDO32Output[MAX_DIO_MODULES];
 310 unsigned int CDIO1616InputInput[MAX_DIO_MODULES]; // Binary input bits
 311 unsigned int CDIO1616Input[MAX_DIO_MODULES]; // Current value of the BO bits
 312 unsigned int CDIO1616Output[MAX_DIO_MODULES]; // Binary output bits
 313 unsigned int CDIO6464InputInput[MAX_DIO_MODULES]; // Binary input bits
 314 unsigned int CDIO6464Input[MAX_DIO_MODULES]; // Current value of the BO bits
 315 unsigned int CDIO6464Output[MAX_DIO_MODULES]; // Binary output bits
 316 unsigned int writeCDIO6464l(CDS_HARDWARE *pHardware, int modNum, unsigned int data);
 317 unsigned int readCDIO6464l(CDS_HARDWARE *pHardware, int modNum);
 318 unsigned int readInputCDIO6464l(CDS_HARDWARE *pHardware, int modNum);
 319 int clock16K = 0;
 320 int out_buf_size = 0; // test checking DAC buffer size
 321 unsigned int cycle_gps_time = 0; // Time at which ADCs triggered
 322 unsigned int cycle_gps_event_time = 0; // Time at which ADCs triggered
 323 unsigned int   cycle_gps_ns = 0;
 324 unsigned int   cycle_gps_event_ns = 0;
 325 unsigned int   gps_receiver_locked = 0; // Lock/unlock flag for GPS time card
 326 unsigned int timeSec = 0;
 327 unsigned int timeSecDiag = 0;
 328 /* 1 - error occured on shmem; 2 - RFM; 3 - Dolphin */
 329 unsigned int ipcErrBits = 0;
 330 int adcTime;			// Used in code cycle timing
 331 int adcHoldTime;		// Stores time between code cycles
 332 int adcHoldTimeMax;		// Stores time between code cycles
 333 int adcHoldTimeEverMax;		// Maximum cycle time recorded
 334 int adcHoldTimeEverMaxWhen;
 335 int startGpsTime;
 336 int adcHoldTimeMin;
 337 int adcHoldTimeAvg;
 338 int adcHoldTimeAvgPerSec;
 339 int usrTime;			// Time spent in user app code
 340 int usrHoldTime;		// Max time spent in user app code
 341 
 342 #if defined(SHMEM_DAQ)
 343 struct rmIpcStr *daqPtr;
 344 #endif
 345 
 346 #if 0
 347 #include <asm/io.h>
 348 #include <genif.h>
 349 
 350 #define COMMDATA_INLINE
 351 #include "commData2.h"
 352 #endif
 353 
 354 int  getGpsTime(unsigned int *tsyncSec, unsigned int *tsyncUsec); 
 355 #include "./feSelectCode.c"
 356 #ifdef NO_RTL
 357 #include "map.c"
 358 #include "fb.c"
 359 #endif
 360 
 361 char daqArea[2*DAQ_DCU_SIZE];		// Space allocation for daqLib buffers
 362 int cpuId = 1;
 363 
 364 #ifdef TIME_MASTER
 365 volatile unsigned int *rfmTime;
 366 #endif
 367 
 368 #ifdef TIME_SLAVE
 369 volatile unsigned int *rfmTime;
 370 #endif
 371 #ifdef IOP_TIME_SLAVE
 372 volatile unsigned int *rfmTime;
 373 #endif
 374 
 375 
 376 #ifdef OVERSAMPLE
 377 
 378 /* Oversamping base rate is 64K */
 379 /* Coeffs for the 2x downsampling (32K system) filter */
 380 static double feCoeff2x[9] =
 381         {0.053628649721183,
 382         -1.25687596603711,    0.57946661417301,    0.00000415782507,    1.00000000000000,
 383         -0.79382359542546,    0.88797791037820,    1.29081406322442,    1.00000000000000};
 384 /* Coeffs for the 4x downsampling (16K system) filter */
 385 static double feCoeff4x[9] =
 386 	{0.014805052402446,  
 387 	-1.71662585474518,    0.78495484219691,   -1.41346289716898,   0.99893884152400,
 388 	-1.68385964238855,    0.93734519457266,    0.00000127375260,   0.99819981588176};
 389 
 390 // New Brian Lantz 4k decimation filter
 391 static double feCoeff16x[9] =
 392          {0.010203728365,
 393          -1.80529410090651,   0.82946925281361,  -1.41324503053632,   0.99863016087226,
 394          -1.83396789879365,   0.87157016192243,  -1.84712607094702,   0.99931484571793};
 395 #if 0
 396 /* Coeffs for the 32x downsampling filter (2K system) */
 397 /* Original Rana coeffs from 40m lab elog */
 398 static double feCoeff32x[9] =
 399         {0.0001104130574447,
 400         -1.97018349613882,    0.97126719875540,   -1.99025960812101,    0.99988962634797,
 401         -1.98715023886379,    0.99107485707332,    2.00000000000000,    1.00000000000000};
 402 #endif
 403 
 404 /* Coeffs for the 32x downsampling filter (2K system) per Brian Lantz May 5, 2009 */
 405 static double feCoeff32x[9] =
 406 	{0.010581064947739,
 407         -1.90444302586137,    0.91078434629894,   -1.96090276933603,    0.99931924465090,
 408         -1.92390910024681,    0.93366146580083,   -1.84652529182276,    0.99866506867980};
 409 
 410 
 411 // History buffers for oversampling filters
 412 double dHistory[96][40];
 413 double dDacHistory[96][40];
 414 
 415 #else
 416 
 417 #define OVERSAMPLE_TIMES 1
 418 #endif
 419 
 420 #define ADC_SAMPLE_COUNT	0x20
 421 #define ADC_DMA_BYTES		0x80
 422 
 423 // Whether run on internal timer (when no ADC cards found)
 424 int run_on_timer = 0;
 425 
 426 // Initial diag reset flag
 427 int initialDiagReset = 1;
 428 int tdsControl[3];
 429 int tdsCount = 0;
 430 
 431 // DIAGNOSTIC_RETURNS_FROM_FE 
 432 #define FE_NO_ERROR		0x0
 433 #define FE_SYNC_ERR		0x1
 434 #define FE_ADC_HOLD_ERR		0x2
 435 #define FE_FB0_NOT_ONLINE	0x4
 436 #define FE_PROC_TIME_ERR	0x8
 437 #define FE_ADC_SYNC_ERR		0xf0
 438 #define FE_FB_AVAIL		0x1
 439 #define FE_FB_ONLINE		0x2
 440 #define FE_MAX_FB_QUE		0x10
 441 #define ADC_TIMEOUT_ERR		0x1
 442 
 443 
 444 // Function to read time from Symmetricom IRIG-B Module ***********************
 445 void lockGpsTime()
 446 {
 447   SYMCOM_REGISTER *timeRead;
 448 	timeRead = (SYMCOM_REGISTER *)cdsPciModules.gps;
 449 	timeRead->TIMEREQ = 1;	// Trigger module to capture time
 450 }
 451 int  getGpsTime(unsigned int *tsyncSec, unsigned int *tsyncUsec) 
 452 {
 453   SYMCOM_REGISTER *timeRead;
 454   unsigned int timeSec,timeNsec,sync;
 455 
 456   if (cdsPciModules.gps) {
 457 	timeRead = (SYMCOM_REGISTER *)cdsPciModules.gps;
 458 	// timeRead->TIMEREQ = 1;	// Trigger module to capture time
 459 	timeSec = timeRead->TIME1;
 460 	timeNsec = timeRead->TIME0;
 461 	// *tsyncSec = timeSec - 252806388;
 462 	*tsyncSec = timeSec - 315964800;
 463 	*tsyncUsec = (timeNsec & 0xfffff); 
 464     // Read seconds, microseconds, nanoseconds
 465     sync = !(timeNsec & (1<<24));
 466   return sync;
 467   //  nsecs = 0xf & (time0 >> 20); // nsecs * 100
 468    // the_time = ((double) time1) + .000001 * (double) msecs  /* + .0000001 * (double) nsecs*/;
 469   }
 470   // printf("%f\n", the_time);
 471   return (0);
 472 }
 473 
 474 //***********************************************************************
 475 // Get current GPS time from TSYNC IRIG-B Rcvr
 476 int  getGpsTimeTsync(unsigned int *tsyncSec, unsigned int *tsyncUsec) {
 477   TSYNC_REGISTER *timeRead;
 478   unsigned int timeSec,timeNsec,sync;
 479   
 480   if (cdsPciModules.gps) {
 481 	timeRead = (TSYNC_REGISTER *)cdsPciModules.gps;
 482 	timeSec = timeRead->BCD_SEC;
 483 	*tsyncSec = timeSec +    31190400;
 484 	timeNsec = timeRead->SUB_SEC;
 485 	*tsyncUsec = ((timeNsec & 0xfffffff) * 5) / 1000; 
 486 	sync = ((timeNsec >> 31) & 0x1) + 1;
 487 	// printf("time = %u %u %d\n",timeSec,(timeNsec & 0xffffff),((timeNsec & 0xffffff)/200));
 488   	return(sync);
 489   }
 490   return(0);
 491 }
 492 
 493 #if 0
 494 //***********************************************************************
 495 // Get current GPS time from SYMCOM IRIG-B Rcvr
 496 // Nanoseconds (hundreds at most) are available as an optional ns parameter
 497 double getGpsTime(unsigned int *ns) {
 498   if(cdsPciModules.gpsType == SYMCOM_RCVR) {
 499 	return getGpsTime1(ns, 0);
 500   }
 501   return(0);
 502 }
 503 
 504 //***********************************************************************
 505 // Get current EVENT time off the card
 506 // Nanoseconds (hundreds at most) are available as an optional ns parameter
 507 double getGpsEventTime(unsigned int *ns) {
 508 	return getGpsTime1(ns, 1);
 509 }
 510 
 511 //***********************************************************************
 512 // Get Gps card microseconds from SYMCOM IRIG-B Rcvr
 513 unsigned int getGpsUsec() {
 514 unsigned int time0,time1;
 515 
 516   if (cdsPciModules.gps) {
 517     // Sample time
 518     cdsPciModules.gps[0] = 1;
 519     // Read microseconds, nanoseconds
 520     time0 = cdsPciModules.gps[SYMCOM_BC635_TIME0/4];
 521     time1 = cdsPciModules.gps[SYMCOM_BC635_TIME1/4];
 522     return 0xfffff & time0; // microseconds
 523   }
 524   return 0;
 525 }
 526 //***********************************************************************
 527 // Get Gps card microseconds from SYMCOM IRIG-B Rcvr
 528 #endif
 529 #ifdef ADC_MASTER
 530 float duotime(int count, float meanVal, float data[])
 531 {
 532   float x,y,sumX,sumY,sumXX,sumXY,msumX;
 533   int ii;
 534   float xInc;
 535   float offset,slope,answer;
 536   float den;
 537 
 538   x = 0;
 539   sumX = 0;
 540   sumY = 0;
 541   sumXX = 0;
 542   sumXY= 0;
 543   xInc = 1000000/CYCLE_PER_SECOND;
 544 
 545 
 546   for(ii=0;ii<count;ii++)
 547   {
 548         y = data[ii];
 549         sumX += x;
 550         sumY += y;
 551         sumXX += x * x;
 552         sumXY += x * y;
 553         x += xInc;
 554 
 555   }
 556         msumX = sumX * -1;
 557         den = (count*sumXX-sumX*sumX);
 558         if(den == 0.0)
 559         {
 560                 // printf("den error\n");
 561                 return(-1000);
 562         }
 563         offset = (msumX*sumXY+sumXX*sumY)/den;
 564         slope = (msumX*sumY+count*sumXY)/den;
 565         if(slope == 0.0)
 566         {
 567                 // printf("slope error\n");
 568                  return(-1000);
 569         }
 570         meanVal -= offset;
 571         // answer = meanVal/slope - 19.7;
 572         // answer = meanVal/slope;
 573         answer = meanVal/slope - 91.552;
 574 #ifdef ADC_MASTER
 575         // answer-= 42.5;
 576 #endif
 577         return(answer);
 578 
 579 }
 580 #endif
 581 
 582 // Cache flushing mumbo jumbo suggested by Thomas Gleixner, it is probably useless
 583 // Did not see any effect
 584   char fp [64*1024];
 585 
 586 
 587 // Get current kernel time (in GPS)
 588 inline unsigned long current_time() {
 589 	struct timespec t;
 590 	extern struct timespec current_kernel_time(void);
 591 	t = current_kernel_time();
 592 	t.tv_sec += - 315964819 + 33;
 593 	return t.tv_sec;
 594 }
 595 
 596 //***********************************************************************
 597 // TASK: fe_start()	
 598 // This routine is the skeleton for all front end code	
 599 //***********************************************************************
 600 void *fe_start(void *arg)
 601 {
 602   int longestWrite2 = 0;
 603   int tempClock[4];
 604   int ii,jj,kk,ll,mm;			// Dummy loop counter variables
 605   static int clock1Min = 0;		// Minute counter (Not Used??)
 606   static int cpuClock[10];		// Code timing diag variables
 607   int adcData[MAX_ADC_MODULES][32];	// ADC raw data
 608   int adcChanErr[16];
 609   int dacChanErr[16];
 610   int adcOF[16];
 611   int dacOF[16];
 612   int limit = 32000;                    // ADC/DAC overflow test value
 613   int offset = 0; //0x8000;
 614   int mask = 0xffff;                    // Bit mask for ADC/DAC read/writes
 615   int num_outs = 16;                    // Number of DAC channels variable
 616 #ifndef ADC_SLAVE
 617   volatile int *packedData;		// Pointer to ADC PCI data space
 618   volatile unsigned int *pDacData;	// Pointer to DAC PCI data space
 619   int timeDiag = 0;			// GPS seconds, passed to EPICS
 620   int wtmin,wtmax;			// Time window for startup on IRIG-B
 621   int dacEnable = 0;
 622   struct timespec next;
 623   int pBits[9] = {1,2,4,8,16,32,64,128,256};
 624 #endif
 625   RFM_FE_COMMS *pEpicsComms;		// Pointer to EPICS shared memory space
 626   int cycleTime;			// Max code cycle time within 1 sec period
 627   int timeHold = 0;
 628   int timeHoldMax = 0;			// Max code cycle time since last diag reset
 629   int myGmError2 = 0;			// Myrinet error variable
 630   // int attemptingReconnect = 0;		// Myrinet reconnect status
 631   int status;				// Typical function return value
 632   float onePps;				// Value of 1PPS signal, if used, for diagnostics
 633   int onePpsHi = 0;			// One PPS diagnostic check
 634   int onePpsTime = 0;			// One PPS diagnostic check
 635   int dcuId;				// DAQ ID number for this process
 636   static int missedCycle = 0;		// Incremented error counter when too many values in ADC FIFO
 637   // int netRetry;				// Myrinet reconnect variable
 638   int diagWord = 0;			// Code diagnostic bit pattern returned to EPICS
 639   int epicsCycle = 0;
 640   int system = 0;
 641   int dac_out = 0;			// Integer value sent to DAC FIFO
 642   int sampleCount = 1;			// Number of ADC samples to take per code cycle
 643   int sync21pps = 0;			// Code startup sync to 1PPS flag
 644   int sync21ppsCycles = 0;		// Number of attempts to sync to 1PPS
 645   int syncSource = SYNC_SRC_NONE;	// Code startup synchronization source
 646   int mxStat = 0;			// Net diags when myrinet express is used
 647   int mxDiag = 0;
 648   int mxDiagR = 0;
 649   unsigned int ns;			// GPS time from IRIG-B
 650   double time;	
 651   unsigned int usec;
 652 // ****** Share data
 653   int ioClock = 0;
 654   int ioClockDac = DAC_PRELOAD_CNT;
 655   int ioMemCntr = 0;
 656   int ioMemCntrDac = DAC_PRELOAD_CNT;
 657   int memCtr = 0;
 658   double dac_in =  0.0;			// DAC value after upsample filtering
 659 
 660   static int dacWriteEnable = 0;
 661   int adcWait;
 662 
 663 #ifdef ADC_MASTER
 664   static float duotone[65536];
 665   static float duotoneDac[65536];
 666   float duotoneTimeDac;
 667   float duotoneTime;
 668   static float duotoneTotal = 0.0;
 669   static float duotoneMean = 0.0;
 670   static float duotoneTotalDac = 0.0;
 671   static float duotoneMeanDac = 0.0;
 672   static rfmDone = 0;
 673   static dacBufSelect = 0;
 674   static dacBufOffset = 0;
 675 #endif
 676 
 677 
 678 #ifdef NO_RTL
 679   int cnt = 0;
 680   unsigned long cpc;
 681   // Flush L1 cache
 682   memset (fp, 0, 64*1024);
 683   memset (fp, 1, 64*1024);
 684   clflush_cache_range ((void *)fp, 64*1024);
 685 #endif
 686 
 687 // Do all of the initalization ***********************************************************************
 688 
 689   /* Init comms with EPICS processor */
 690   pEpicsComms = (RFM_FE_COMMS *)_epics_shm;
 691   pLocalEpics = (CDS_EPICS *)&pEpicsComms->epicsSpace;
 692 
 693 #ifdef OVERSAMPLE
 694   // Zero out filter histories
 695   memset(dHistory, 0, sizeof(dHistory));
 696   memset(dDacHistory, 0, sizeof(dDacHistory));
 697 #endif
 698 
 699   // Zero out DAC outputs
 700   for (ii = 0; ii < MAX_DAC_MODULES; ii++)
 701     for (jj = 0; jj < 16; jj++) {
 702  	dacOut[ii][jj] = 0.0;
 703  	dacOutUsed[ii][jj] = 0;
 704     }
 705 
 706   // Set pointers to filter module data buffers
 707     pDsp[system] = (FILT_MOD *)(&pEpicsComms->dspSpace);
 708     pCoeff[system] = (VME_COEF *)(&pEpicsComms->coeffSpace);
 709     dspPtr[system] = dsp;
 710 
 711   // Clear the FE reset which comes from Epics
 712   pLocalEpics->epicsInput.vmeReset = 0;
 713 
 714 #ifndef ADC_SLAVE
 715   // Look for DIO card or IRIG-B Card
 716   // if Contec 1616 BIO present, TDS slave will be used for timing.
 717   if(cdsPciModules.cDio1616lCount) syncSource = SYNC_SRC_TDS;
 718   // if IRIG-B card present, code will use it for startup synchonization
 719   if(cdsPciModules.gpsType && (syncSource == SYNC_SRC_NONE)) 
 720 	syncSource = SYNC_SRC_IRIG_B;
 721   	// If no IRIG-B card, will try 1PPS on ADC[0][31] later
 722   if(syncSource == SYNC_SRC_NONE) 
 723 	syncSource = SYNC_SRC_1PPS;
 724 #else
 725    // SLAVE processes get sync from ADC_MASTER
 726    syncSource = SYNC_SRC_MASTER;
 727 #endif
 728 
 729 printf("Sync source = %d\n",syncSource);
 730 
 731 
 732   // Do not proceed until EPICS has had a BURT restore *******************************
 733 #ifdef NO_RTL
 734   printf("Waiting for EPICS BURT Restore = %d\n", pLocalEpics->epicsInput.burtRestore);
 735   cnt = 0;
 736 #else
 737   if(cdsPciModules.gpsType == SYMCOM_RCVR) 
 738   {
 739   	gps_receiver_locked = getGpsTime(&timeSec,&usec);
 740         printf("Found SYMCOM IRIG-B - Time is %d and %d us \n", time, usec);
 741   }
 742   if(cdsPciModules.gpsType == SYMCOM_RCVR) 
 743   {
 744   	gps_receiver_locked = getGpsTime(&timeSec,&usec);
 745         printf("Found SYMCOM IRIG-B - Time is %f and %d ns 0x%x\n", time, ns);
 746   }
 747   if(cdsPciModules.gpsType == TSYNC_RCVR) 
 748   {
 749   	gps_receiver_locked = getGpsTimeTsync(&timeSec,&usec);
 750         printf("Found TSYNC IRIG-B - Time is %d and %d us 0x%x\n", timeSec, usec);
 751   }
 752   printf("Waiting for EPICS BURT \n");
 753 #endif
 754   do{
 755 #ifdef NO_RTL
 756 	udelay(20000);
 757         udelay(20000);
 758         udelay(20000);
 759   	printf("Waiting for EPICS BURT %d\n", cnt++);
 760 	cpu_relax();
 761 #else
 762 	usleep(1000000);
 763 #endif
 764   }while(!pLocalEpics->epicsInput.burtRestore);
 765 
 766   printf("BURT Restore Complete\n");
 767 
 768 // BURT has completed *******************************************************************
 769 
 770 // Read in all Filter Module EPICS settings
 771   for (system = 0; system < NUM_SYSTEMS; system++)
 772   {
 773     for(ii=0;ii<END_OF_DAQ_BLOCK;ii++)
 774     {
 775 	updateEpics(ii, dspPtr[system], pDsp[system],
 776 		    &dspCoeff[system], pCoeff[system]);
 777     }
 778   }
 779 
 780   // Need this FE dcuId to make connection to FB
 781   dcuId = pLocalEpics->epicsInput.dcuId;
 782 
 783   // Reset timing diagnostics
 784   pLocalEpics->epicsOutput.diagWord = 0;
 785   pLocalEpics->epicsOutput.timeDiag = 0;
 786   pLocalEpics->epicsOutput.timeErr = syncSource;
 787 
 788 //   Initialize filter banks  *********************************************
 789   for (system = 0; system < NUM_SYSTEMS; system++) {
 790     for(ii=0;ii<MAX_MODULES;ii++){
 791       for(jj=0;jj<FILTERS;jj++){
 792         for(kk=0;kk<MAX_COEFFS;kk++){
 793           dspCoeff[system].coeffs[ii].filtCoeff[jj][kk] = 0.0;
 794         }
 795         dspCoeff[system].coeffs[ii].filtSections[jj] = 0;
 796       }
 797     }
 798   }
 799 
 800   // Initialize all filter module excitation signals to zero 
 801   for (system = 0; system < NUM_SYSTEMS; system++)
 802     for(ii=0;ii<MAX_MODULES;ii++)
 803        dsp[system].data[ii].exciteInput = 0.0;
 804 
 805 
 806   /* Initialize DSP filter bank values */
 807   for (system = 0; system < NUM_SYSTEMS; system++)
 808     if (initVars(dsp + system, pDsp[system], dspCoeff + system, MAX_MODULES, pCoeff[system])) {
 809     	printf("Filter module init failed, exiting\n");
 810 	return 0;
 811     }
 812 
 813   printf("Initialized servo control parameters.\n");
 814 
 815 #ifdef NO_RTL
 816 udelay(1000);
 817 #endif
 818 
 819 // Initialize DAQ variable/software **************************************************
 820 #if !defined(NO_DAQ) && !defined(IOP_TASK)
 821   /* Set data range limits for daqLib routine */
 822 #if defined(SERVO2K) || defined(SERVO4K)
 823   daq.filtExMin = 20001;
 824   daq.filtTpMin = 30001;
 825 #else
 826   daq.filtExMin = 1;
 827   daq.filtTpMin = 10001;
 828 #endif
 829   daq.filtExMax = daq.filtExMin + MAX_MODULES;
 830   daq.filtExSize = MAX_MODULES;
 831   daq.xExMin = daq.filtExMax;
 832   daq.xExMax = daq.xExMin + 50;
 833   daq.filtTpMax = daq.filtTpMin + MAX_MODULES * 3;
 834   daq.filtTpSize = MAX_MODULES * 3;
 835   daq.xTpMin = daq.filtTpMax;
 836   daq.xTpMax = daq.xTpMin + 500;
 837 
 838   printf("DAQ Ex Min/Max = %d %d\n",daq.filtExMin,daq.filtExMax);
 839   printf("DAQ XEx Min/Max = %d %d\n",daq.xExMin,daq.xExMax);
 840   printf("DAQ Tp Min/Max = %d %d\n",daq.filtTpMin,daq.filtTpMax);
 841   printf("DAQ XTp Min/Max = %d %d\n",daq.xTpMin,daq.xTpMax);
 842 
 843   // Assign DAC testpoint pointers
 844   for (ii = 0; ii <  cdsPciModules.dacCount; ii++)
 845 	for (jj = 0; jj < 16; jj++) // 16 per DAC regardless of the actual
 846 		testpoint[16 * ii + jj] = floatDacOut + 16 * ii + jj;
 847 
 848   // Zero out storage
 849   memset(floatDacOut, 0, sizeof(floatDacOut));
 850 
 851 #endif
 852   pLocalEpics->epicsOutput.diags[FE_DIAGS_IPC_STAT] = 0;
 853   pLocalEpics->epicsOutput.diags[FE_DIAGS_FB_NET_STAT] = 0;
 854 
 855 
 856 #if !defined(NO_DAQ) && !defined(IOP_TASK)
 857   // Initialize DAQ function
 858   status = daqWrite(0,dcuId,daq,DAQ_RATE,testpoint,dspPtr[0],0,pLocalEpics->epicsOutput.gdsMon,xExc);
 859   if(status == -1) 
 860   {
 861     printf("DAQ init failed -- exiting\n");
 862     vmeDone = 1;
 863     return(0);
 864   }
 865 #endif
 866 
 867 #ifndef ADC_MASTER
 868 	// SLAVE units read/write their own DIO
 869 	// MASTER units ignore DIO for speed reasons
 870 	// Read Dio card initial values *************************************
 871      for(kk=0;kk<cdsPciModules.doCount;kk++)
 872      {
 873 	ii = cdsPciModules.doInstance[kk];
 874 	if(cdsPciModules.doType[kk] == ACS_8DIO)
 875 	{
 876 	  if (rioReadOps[ii] & 1) rioInputInput[ii] = readIiroDio(&cdsPciModules, kk) & 0xff;
 877 	  if (rioReadOps[ii] & 2) rioInputOutput[ii] = readIiroDioOutput(&cdsPciModules, kk) & 0xff;
 878 	} else if(cdsPciModules.doType[kk] == ACS_16DIO) {
 879   	  rioInput1[ii] = readIiroDio1(&cdsPciModules, kk) & 0xffff;
 880 	} else if (cdsPciModules.doType[kk] == CON_32DO) {
 881   	  CDO32Input[ii] = readCDO32l(&cdsPciModules, kk);
 882 	} else if (cdsPciModules.doType[kk] == CON_1616DIO) {
 883   	  CDIO1616Input[ii] = readCDIO1616l(&cdsPciModules, kk);
 884 	} else if (cdsPciModules.doType[kk] == CON_6464DIO) {
 885   	  CDIO6464Input[ii] = readCDIO6464l(&cdsPciModules, kk);
 886 	} else if(cdsPciModules.doType[kk] == ACS_24DIO) {
 887   	  dioInput[ii] = readDio(&cdsPciModules, kk);
 888 	}
 889      }
 890 #endif
 891 
 892 
 893   // Clear the code exit flag
 894   vmeDone = 0;
 895 
 896   // Initialize user application software ************************************
 897   printf("Calling feCode() to initialize\n");
 898   feCode(clock16K,dWord,dacOut,dspPtr[0],&dspCoeff[0],pLocalEpics,1);
 899 
 900   printf("entering the loop\n");
 901 
 902   // Clear a couple of timing diags.
 903   adcHoldTime = 0;
 904   adcHoldTimeMax = 0;
 905   adcHoldTimeEverMax = 0;
 906   adcHoldTimeEverMaxWhen = 0;
 907   startGpsTime = 0;
 908   adcHoldTimeMin = 0xffff;
 909   adcHoldTimeAvg = 0;
 910   usrHoldTime = 0;
 911   missedCycle = 0;
 912 
 913   // Initialize the ADC 
 914 #ifndef ADC_SLAVE
 915   for(jj=0;jj<cdsPciModules.adcCount;jj++)
 916   {
 917 	  // Setup the DMA registers
 918 	  status = gsaAdcDma1(jj,cdsPciModules.adcType[jj],ADC_DMA_BYTES);
 919 	  // Preload input memory with dummy variables to test that new ADC data has arrived.
 920 	  packedData = (int *)cdsPciModules.pci_adc[jj];
 921 	  // Write a dummy 0 to first ADC channel location
 922 	  // This location should never be zero when the ADC writes data as it should always
 923 	  // have an upper bit set indicating channel 0.
 924           *packedData = 0x0;
 925           if (cdsPciModules.adcType[jj] == GSC_16AISS8AO4
 926               || cdsPciModules.adcType[jj] == GSC_18AISS8AO8) {
 927                  packedData += 3;
 928           } else packedData += 31;
 929 	  // Write a number into the last channel which the ADC should never write ie no
 930 	  // upper bits should be set in channel 31.
 931           *packedData = 0x110000;
 932 	  // Set ADC Present Flag
 933   	  pLocalEpics->epicsOutput.statAdc[jj] = 1;
 934   }
 935   printf("ADC setup complete \n");
 936 #endif
 937 #ifdef ADC_SLAVE
 938   for(jj=0;jj<cdsPciModules.adcCount;jj++)
 939   {
 940   	  pLocalEpics->epicsOutput.statAdc[jj] = 1;
 941   }
 942 #endif
 943 
 944 #ifndef ADC_SLAVE
 945   // Initialize the DAC module variables
 946   for(jj = 0; jj < cdsPciModules.dacCount; jj++) {
 947   	pLocalEpics->epicsOutput.statDac[jj] = 1;
 948         pDacData = (unsigned int *) cdsPciModules.pci_dac[jj];
 949 	// Arm DAC DMA for full data size
 950 	status = gsaDacDma1(jj, cdsPciModules.dacType[jj]);
 951   }
 952   printf("DAC setup complete \n");
 953 #endif
 954 
 955   
 956 #ifdef NO_RTL
 957 
 958 #ifndef NO_CPU_DISABLE
 959   // Take the CPU away from Linux
 960   //__cpu_disable(); 
 961 #endif
 962 #endif
 963 
 964 #ifndef ADC_SLAVE
 965   if (!run_on_timer) {
 966   switch(syncSource)
 967   {
 968 	case SYNC_SRC_TDS:
 969 		// Turn off the ADC/DAC clocks
 970 		for(ii=0;ii<tdsCount;ii++)
 971 		{
 972 		CDIO1616Output[ii] = TDS_STOP_CLOCKS;
 973 		CDIO1616Input[ii] = writeCDIO1616l(&cdsPciModules, tdsControl[ii], CDIO1616Output[ii]);
 974 		printf("writing BIO %d\n",tdsControl[ii]);
 975 		}
 976 #ifdef NO_RTL
 977 		udelay(20000);
 978 		udelay(20000);
 979 #else
 980 		usleep(40000);
 981 #endif
 982 		// Arm ADC modules
 983     		gsaAdcTrigger(cdsPciModules.adcCount,cdsPciModules.adcType);
 984 		// Arm DAC outputs
 985 		gsaDacTrigger(&cdsPciModules);
 986 		// Set synched flag so later code will not check for 1PPS
 987 		sync21pps = 1;
 988 #ifdef NO_RTL
 989 		udelay(20000);
 990 		udelay(20000);
 991 #else
 992 		usleep(40000);
 993 #endif
 994 		// Start ADC/DAC clocks
 995 		// CDIO1616Output[tdsControl] = 0x7B00000;
 996 		for(ii=0;ii<tdsCount;ii++)
 997 		{
 998 		CDIO1616Output[ii] = TDS_START_ADC_NEG_DAC_POS;
 999 		CDIO1616Input[ii] = writeCDIO1616l(&cdsPciModules, tdsControl[ii], CDIO1616Output[ii]);
1000 		}
1001 		break;
1002 	case SYNC_SRC_IRIG_B:
1003 		 // If IRIG-B card present, use it for startup synchronization
1004 		wtmax = 20;
1005 		wtmin = 5;
1006 		printf("Waiting until usec = %d to start the ADCs\n", wtmin);
1007 		do{
1008 			if(cdsPciModules.gpsType == SYMCOM_RCVR) gps_receiver_locked = getGpsTime(&timeSec,&usec);
1009 			if(cdsPciModules.gpsType == TSYNC_RCVR) gps_receiver_locked = getGpsTimeTsync(&timeSec,&usec);
1010 		}while ((usec < wtmin) || (usec > wtmax));
1011 		// Arm ADC modules
1012 		gsaAdcTrigger(cdsPciModules.adcCount,cdsPciModules.adcType);
1013 		// Start clocking the DAC outputs
1014 		gsaDacTrigger(&cdsPciModules);
1015 		// Set synched flag so later code will not check for 1PPS
1016 		sync21pps = 1;
1017 		// Send IRIG-B locked/not locked diagnostic info
1018 		if(!gps_receiver_locked)pLocalEpics->epicsOutput.timeErr |= TIME_ERR_IRIGB;
1019 		printf("Running time %d us\n", usec);
1020 	  	printf("Triggered the DAC\n");
1021 		break;
1022 	case SYNC_SRC_1PPS:
1023 		// Arm ADC modules
1024 		gsaAdcTrigger(cdsPciModules.adcCount,cdsPciModules.adcType);
1025 		// Start clocking the DAC outputs
1026 		gsaDacTrigger(&cdsPciModules);
1027 		break;
1028 	default: {
1029 		    // IRIG-B card not found, so use CPU time to get close to 1PPS on startup
1030 			// Pause until this second ends
1031 		#ifdef NO_RTL
1032 		/*
1033 			:TODO:
1034 			wait_delay = nano2count(WAIT_DELAY);
1035 			period     = nano2count(PERIOD);
1036 			for(msg = 0; msg < MAXDIM; msg++) {
1037 				a[msg] = b[msg] = 3.141592;
1038 			}
1039 			rtai_cli();
1040 			aim_time  = rt_get_time();
1041 			sync_time = aim_time + wait_delay;
1042 		*/
1043 #ifdef TIME_SLAVE
1044 // sync up with the time master on its gps time
1045 	  unsigned long d = cdsPciModules.dolphin[0][1];
1046 
1047  	  if (boot_cpu_has(X86_FEATURE_MWAIT)) {
1048 	    for (;;) {
1049 		         if (cdsPciModules.dolphin[0][1] != d) break;
1050 			 __monitor((void *)&cdsPciModules.dolphin[0][1], 0, 0);
1051 		         if (cdsPciModules.dolphin[0][1] != d) break;
1052 			 __mwait(0, 0);
1053 	    }
1054  	  } else {
1055             do {
1056 #ifdef NO_RTL
1057 		udelay(1);
1058 #else
1059                 usleep(1);
1060 #endif
1061             } while(cdsPciModules.dolphin[0][1] != d);
1062 	  }
1063 #endif
1064 	  #ifdef RFM_TIME_SLAVE
1065 	  for(;((volatile long *)(cdsPciModules.pci_rfm[0]))[0] != 0;) udelay(1);
1066 	  timeSec = ((volatile long *)(cdsPciModules.pci_rfm[0]))[1];
1067 	  timeSec --;
1068 	  #endif
1069 		#else
1070 			clock_gettime(CLOCK_REALTIME, &next);
1071 			// printf("Start time %ld s %ld ns\n", next.tv_sec, next.tv_nsec);
1072 			next.tv_nsec = 0;
1073 			next.tv_sec += 1;
1074 			clock_nanosleep(CLOCK_REALTIME, TIMER_ABSTIME, &next, NULL);
1075 			clock_gettime(CLOCK_REALTIME, &next);
1076 			// printf("Running time without IRIGb%ld s %ld ns\n", next.tv_sec, next.tv_nsec);
1077 		#endif
1078 		break;
1079 	}
1080   }
1081   }
1082 
1083 
1084   if (run_on_timer) {
1085     printf("*******************************\n");
1086     printf("*     Running on timer!       *\n");
1087     printf("*******************************\n");
1088   } else {
1089     printf("Triggered the ADC\n");
1090   }
1091 #endif
1092 #ifdef ADC_SLAVE
1093 	// SLAVE needs to sync with MASTER by looking for cycle 0 count in ipc memory
1094 	// Find memory buffer of first ADC to be used in SLAVE application.
1095         ll = cdsPciModules.adcConfig[0];
1096         printf("waiting to sync %d\n",ioMemData->iodata[ll][0].cycle);
1097         rdtscl(cpuClock[0]);
1098 
1099  	if (boot_cpu_has(X86_FEATURE_MWAIT)) {
1100 	  for(;;) {
1101 	    if (ioMemData->iodata[ll][0].cycle == 0) break;
1102 	    __monitor((void *)&(ioMemData->iodata[ll][0].cycle), 0, 0);
1103 	    if (ioMemData->iodata[ll][0].cycle == 0) break;
1104 	    __mwait(0, 0);
1105 	  }
1106  	} else {
1107 	  // Spin until cycle 0 detected in first ADC buffer location.
1108           do {
1109 #ifdef NO_RTL
1110 		udelay(1);
1111 #else
1112                 usleep(1);
1113 #endif
1114           } while(ioMemData->iodata[ll][0].cycle != 0);
1115 	}
1116         timeSec = ioMemData->iodata[ll][0].timeSec;
1117 
1118         rdtscl(cpuClock[1]);
1119         cycleTime = (cpuClock[1] - cpuClock[0])/CPURATE;
1120         printf("Synched %d\n",cycleTime);
1121 	// Need to set sync21pps so code will not try to sync with 1pps pulse later.
1122 	sync21pps=1;
1123 	// Get GPS seconds from MASTER
1124 	timeSec = ioMemData->gpsSecond;
1125         pLocalEpics->epicsOutput.timeDiag = timeSec;
1126 	// Decrement GPS seconds as it will be incremented on first read cycle.
1127 	timeSec --;
1128 
1129 #endif
1130   onePpsTime = clock16K;
1131   timeSec = current_time() -1;
1132   if(cdsPciModules.gpsType == SYMCOM_RCVR)
1133   {
1134   	// time = getGpsTime(&ns);
1135 	// timeSec = time - 252806386;
1136   }
1137   if(cdsPciModules.gpsType == TSYNC_RCVR) 
1138   {
1139 	// gps_receiver_locked = getGpsTimeTsync(&timeSec,&usec);
1140 	// timeSec += 284083219;
1141 	// timeSec += 0;
1142   }
1143 #ifdef TIME_SLAVE
1144 	timeSec = *rfmTime;
1145 #endif
1146 
1147   rdtscl(adcTime);
1148 
1149   // **********************************************************************************************
1150   // Enter the infinite FE control loop  **********************************************************
1151   // **********************************************************************************************
1152 #ifdef NO_RTL
1153   // Calculate how many CPU cycles per code cycle
1154   cpc = cpu_khz * 1000;
1155   cpc /= CYCLE_PER_SECOND;
1156 #endif
1157 
1158   while(!vmeDone){ 	// Run forever until user hits reset
1159 
1160   	if (run_on_timer) {  // NO ADC present, so run on CPU realtime clock
1161 	  // Pause until next cycle begins
1162 	  if (clock16K == 0) {
1163 	    	//printf("awgtpman gps = %d local = %d\n", pEpicsComms->padSpace.awgtpman_gps, timeSec);
1164 	  	pLocalEpics->epicsOutput.diags[9] = (pEpicsComms->padSpace.awgtpman_gps != timeSec);
1165 	  }
1166 #ifdef NO_RTL
1167 #if !defined (TIME_SLAVE) && !defined (RFM_TIME_SLAVE)
1168 	  // This is local CPU timer (no ADCs)
1169 	  // advance to the next cycle polling CPU cycles and microsleeping
1170   	  int clk, clk1;
1171 	  rdtscl(clk);
1172 	  clk += cpc;
1173 	  for(;;) {
1174 	  	rdtscl(clk1);
1175 		if (clk1 >= clk) break;
1176 		udelay(1);
1177 	  }
1178 #else
1179 #ifdef RFM_TIME_SLAVE
1180 	  unsigned long d = ((volatile long *)(cdsPciModules.pci_rfm[0]))[0];
1181 	  d=clock16K;
1182 	  for(;((volatile long *)(cdsPciModules.pci_rfm[0]))[0] != d;) udelay(1);
1183 	  timeSec = ((volatile long *)(cdsPciModules.pci_rfm[0]))[1];
1184 #elif defined(TIME_SLAVE)
1185 	  // sync up with the time master on its gps time
1186 	  //
1187 	  unsigned long d = 0;
1188           //if (iop_rfm_valid) d = cdsPciModules.dolphin[0][1];
1189 	  d = clock16K;
1190 	  for(;iop_rfm_valid? cdsPciModules.dolphin[0][1] != d: 0;) udelay(1);
1191 #endif
1192 	    ioMemCntr = (clock16K % 64);
1193 	    for(ii=0;ii<32;ii++)
1194 	    {
1195 		ioMemData->iodata[0][ioMemCntr].data[ii] = clock16K/4;
1196 		ioMemData->iodata[1][ioMemCntr].data[ii] = clock16K/4;
1197 	    }
1198 	    // Write GPS time and cycle count as indicator to slave that adc data is ready
1199 	    ioMemData->gpsSecond = timeSec;
1200 	    ioMemData->iodata[0][ioMemCntr].timeSec = timeSec;;
1201 	    ioMemData->iodata[1][ioMemCntr].timeSec = timeSec;;
1202 	    ioMemData->iodata[0][ioMemCntr].cycle = clock16K;
1203 	    ioMemData->iodata[1][ioMemCntr].cycle = clock16K;
1204 #if 0
1205 	  for (;;) {
1206 		         if (cdsPciModules.dolphin[0][1] != d) break;
1207 			 __monitor((void *)&cdsPciModules.dolphin[0][1], 0, 0);
1208 		         if (cdsPciModules.dolphin[0][1] != d) break;
1209 			 __mwait(0, 0);
1210 	  }
1211 #endif
1212 	//if (dolphin_memory_read[1] != d+1) printk("dolphin cycle jump from %d to %d\n", d, dolphin_memory_read[1]);
1213 #endif
1214 #else
1215     	  struct timespec next;
1216     	  clock_gettime(CLOCK_REALTIME, &next);
1217 	  if (clock16K == 0) {
1218  	    next.tv_nsec = 0;
1219 	    next.tv_sec += 1;
1220 	  } else {
1221     	    next.tv_nsec = 1000000000 / CYCLE_PER_SECOND * clock16K;
1222 	  }
1223           clock_nanosleep(CLOCK_REALTIME, TIMER_ABSTIME, &next, NULL);
1224 #endif
1225 	  rdtscl(cpuClock[0]);
1226 #if defined(RFM_TIME_SLAVE) || defined(TIME_SLAVE)
1227 #ifndef ADC_SLAVE
1228 	  // Write GPS time and cycle count as indicator to slave that adc data is ready
1229 	  ioMemData->gpsSecond = timeSec;
1230 	  ioMemData->iodata[0][0].cycle = clock16K;
1231 	  #ifndef RFM_TIME_SLAVE
1232           if(clock16K == 0) timeSec++;
1233 	  #endif
1234 #endif
1235 #endif
1236          if(clock16K == 0) {
1237 
1238 #ifdef TIME_SLAVE
1239 	  if (iop_rfm_valid) timeSec = *rfmTime;
1240 	//*((volatile unsigned int *)dolphin_memory) = timeSec ++;
1241 #else
1242 	  // Increment GPS second on cycle 0
1243           // timeSec ++;
1244 #endif
1245           pLocalEpics->epicsOutput.timeDiag = timeSec;
1246 	  }
1247 	} else {
1248 	// NORMAL OPERATION -- Wait for ADC data ready
1249 	// On startup, only want to read one sample such that first cycle
1250 	// coincides with GPS 1PPS. Thereafter, sampleCount will be 
1251 	// increased to appropriate number of 65536 s/sec to match desired
1252 	// code rate eg 32 samples each time thru before proceeding to match 2048 system.
1253 	// **********************************************************************************************************
1254 #if 0
1255 		if (cdsPciModules.pci_rfm[0]) rfm55DMA(&cdsPciModules,0,(clock16K % 64));
1256 		if (cdsPciModules.pci_rfm[1]) rfm55DMA(&cdsPciModules,1,(clock16K % 64));
1257 #endif
1258        if(clock16K == 0)
1259         {
1260 	  //printf("awgtpman gps = %d local = %d\n", pEpicsComms->padSpace.awgtpman_gps, timeSec);
1261 	  pLocalEpics->epicsOutput.diags[9] = (pEpicsComms->padSpace.awgtpman_gps != timeSec);
1262 
1263 	  // Increment GPS second on cycle 0
1264 #ifndef ADC_SLAVE
1265           timeSec ++;
1266           pLocalEpics->epicsOutput.timeDiag = timeSec;
1267 	  // printf("cycle = %d  time = %d\n",clock16K,timeSec);
1268 #endif
1269 #ifdef TIME_MASTER
1270 	  // Update time on RFM if this is GPS time master
1271           rdtscl(tempClock[0]);
1272 	  *rfmTime = timeSec;
1273 	  //sci_flush(&sci_dev_info, 0);
1274           rdtscl(tempClock[1]);
1275   	  clflush_cache_range (cdsPciModules.dolphin[1], 8);
1276 #endif
1277 	}
1278         for(ll=0;ll<sampleCount;ll++)
1279         {
1280 #ifndef ADC_SLAVE
1281 		// Read ADC data
1282                for(jj=0;jj<cdsPciModules.adcCount;jj++)
1283 		{
1284 		    // Check ADC DMA has completed
1285 		    // This is detected when last channel in memory no longer contains the
1286 		    // dummy variable written during initialization and reset after the read.
1287 		    packedData = (int *)cdsPciModules.pci_adc[jj];
1288                	    packedData += 31;
1289                     kk = 0;
1290 		
1291 		    rdtscl(cpuClock[8]);
1292 
1293 #if 0
1294 		    // Monitor the first ADC
1295 		    if (jj == 0) {
1296 		       for (;;) {
1297 		         if (*packedData != 0x110000) break;
1298 			 __monitor((void *)packedData, 0, 0);
1299 		         if (*packedData != 0x110000) break;
1300 			 __mwait(0, 0);
1301 		       }
1302 		       rdtscl(cpuClock[9]);
1303 		       adcWait = (cpuClock[9] - cpuClock[8])/CPURATE;
1304 		    } else 
1305 #endif
1306                     do {
1307                         kk ++;
1308 			// Need to delay if not ready as constant banging of the input register
1309 			// will slow down the ADC DMA.
1310 			if(*packedData == 0x110000) {
1311 //#ifdef NO_RTL
1312 				//udelay(1);
1313 //#else
1314 				// if(jj==0) usleep(0);
1315 		    		rdtscl(cpuClock[9]);
1316 				adcWait = (cpuClock[9] - cpuClock[8])/CPURATE;
1317 #ifndef RFM_DIRECT_READ
1318 #ifdef ADC_MASTER
1319 				if(((cpuClock[9] - cpuClock[0])/CPURATE > 10) && (!rfmDone))
1320 				{
1321 					if (cdsPciModules.pci_rfm[0]) rfm55DMA(&cdsPciModules,0,(clock16K % 64));
1322 					if (cdsPciModules.pci_rfm[1]) rfm55DMA(&cdsPciModules,1,(clock16K % 64));
1323 					rfmDone = 1;
1324 				}
1325 #endif
1326 #endif
1327 //#endif
1328 			}
1329 			// Allow 1msec for data to be ready (should never take that long).
1330                     }while((*packedData == 0x110000) && (adcWait < 1000000));
1331 
1332 #ifdef ADC_MASTER
1333 #ifndef RFM_DIRECT_READ
1334 				if(!rfmDone)
1335 				{
1336 					if (cdsPciModules.pci_rfm[0]) rfm55DMA(&cdsPciModules,0,(clock16K % 64));
1337 					if (cdsPciModules.pci_rfm[1]) rfm55DMA(&cdsPciModules,1,(clock16K % 64));
1338 				}
1339 #endif
1340 		rfmDone = 0;
1341 #endif
1342 
1343 		    // If data not ready in time, abort
1344 		    // Either the clock is missing or code is running too slow and ADC FIFO
1345 		    // is overflowing.
1346 		    if (adcWait >= 1000000) {
1347                         stop_working_threads = 1;
1348 	  		pLocalEpics->epicsOutput.diagWord |= ADC_TIMEOUT_ERR;
1349                         printf("timeout %d %d \n",jj,adcWait);
1350                     }
1351 		    if(jj == 0) 
1352 		    {
1353 			// Capture cpu clock for cpu meter diagnostics
1354 			rdtscl(cpuClock[0]);
1355 #ifdef ADC_MASTER
1356 			// Write data to DAC modules
1357 			// This is done here after 1st ADC ready to allow max time to
1358 			// load DAC values prior to next 65K clock
1359 			for(mm=0;mm<cdsPciModules.dacCount;mm++)
1360 	   		   if(dacWriteEnable > 4) gsaDacDma2(mm,cdsPciModules.dacType[mm],dacBufOffset);
1361 			// if(clock16K == 65535) 
1362 			if(clock16K == 0) 
1363 			{
1364 				// if SymCom type, just do write to lock current time and read later
1365 				// This save a couple three microseconds here
1366 				if(cdsPciModules.gpsType == SYMCOM_RCVR) lockGpsTime();
1367 				if(cdsPciModules.gpsType == TSYNC_RCVR) 
1368 				{
1369 					gps_receiver_locked = getGpsTimeTsync(&timeSec,&usec);
1370 					pLocalEpics->epicsOutput.diags[FE_DIAGS_IRIGB_TIME] = usec;
1371 				}
1372 #ifdef IOP_TIME_SLAVE_RFM
1373 	  timeSec = ((volatile long *)(cdsPciModules.pci_rfm[0]))[1];
1374 	  timeSec ++;
1375 #endif
1376 			}
1377 			
1378 #ifdef IOP_TIME_SLAVE
1379 	  		if (iop_rfm_valid) timeSec = *rfmTime;
1380 #endif
1381 #endif
1382 		    }
1383 #ifdef TIME_MASTER
1384 		if (iop_rfm_valid) {
1385 			//*rfmTime = timeSec;
1386           		rdtscl(tempClock[2]);
1387 			cdsPciModules.dolphin[1][1] = clock16K;
1388 	  		//sci_flush(&sci_dev_info, 0);
1389           		rdtscl(tempClock[3]);
1390   			clflush_cache_range (cdsPciModules.dolphin[1] + 1, 8);
1391 		}
1392 		if (cdsPciModules.pci_rfm[0]) {
1393 		    	((volatile long *)(cdsPciModules.pci_rfm[0]))[1] = timeSec;
1394   			clflush_cache_range (((volatile long *)(cdsPciModules.pci_rfm[0])) + 1, 8);
1395 		    	((volatile long *)(cdsPciModules.pci_rfm[0]))[0] = clock16K;
1396   			clflush_cache_range (((volatile long *)(cdsPciModules.pci_rfm[0])), 8);
1397 		}
1398 		if (cdsPciModules.pci_rfm[1]) {
1399 		    	((volatile long *)(cdsPciModules.pci_rfm[1]))[1] = timeSec;
1400   			clflush_cache_range (((volatile long *)(cdsPciModules.pci_rfm[1])) + 1, 8);
1401 		    	((volatile long *)(cdsPciModules.pci_rfm[1]))[0] = clock16K;
1402   			clflush_cache_range (((volatile long *)(cdsPciModules.pci_rfm[1])), 8);
1403 		}
1404 #endif
1405 
1406                     // Read adc data
1407                     packedData = (int *)cdsPciModules.pci_adc[jj];
1408 		    // FIrst, and only first, channel should have upper bit marker set.
1409                     // Return 0x10 if first ADC channel does not have sync bit set
1410                     if(*packedData & 0xf0000) 
1411 		    {
1412 			status = 0;
1413                     } else {
1414 			 status = 16;
1415   			 adcChanErr[jj] = 1;
1416 	 	    }	
1417 
1418                     limit = 32700;
1419 		    // Various ADC models have different number of channels/data bits
1420                     offset = 0x8000;
1421                     mask = 0xffff;
1422                     num_outs = 32;
1423 #if 0
1424 		// In this version, the following two ADC models are not fully supported.
1425 		// This bit of code is left behind in case there is a need to reintroduce it.
1426                     if (cdsPciModules.adcType[jj] == GSC_18AISS8AO8) {
1427 			limit *= 4; // 18 bit limit
1428 			offset = 0x20000; // Data coding offset in 18-bit DAC
1429 			mask = 0x3ffff;
1430 			num_outs = 8;
1431                     }
1432                     if (cdsPciModules.adcType[jj] == GSC_16AISS8AO4) {
1433 			num_outs = 4;
1434                     }
1435 #endif
1436 #ifdef ADC_MASTER
1437 		    // Determine next ipc memory location to load ADC data
1438 		    ioMemCntr = (clock16K % 64);
1439 #endif
1440                     // Read adc data from PCI mapped memory into local variables
1441                     for(ii=0;ii<num_outs;ii++)
1442                     {
1443 			// adcData is the integer representation of the ADC data
1444 			adcData[jj][ii] = (*packedData & mask);
1445 			adcData[jj][ii]  -= offset;
1446 			// dWord is the double representation of the ADC data
1447 			// This is the value used by the rest of the code calculations.
1448 			dWord[jj][ii] = adcData[jj][ii];
1449 #ifdef ADC_MASTER
1450 			// Load adc value into ipc memory buffer
1451 			ioMemData->iodata[jj][ioMemCntr].data[ii] = adcData[jj][ii];
1452 #endif
1453 #ifdef OVERSAMPLE
1454 			// Downsample filter only used channels to save time
1455 			// This is defined in user C code
1456 			if (dWordUsed[jj][ii]) {
1457 				dWord[jj][ii] = iir_filter(dWord[jj][ii],FE_OVERSAMPLE_COEFF,2,&dHistory[ii+jj*32][0]);
1458 			}
1459 #endif
1460 			packedData ++;
1461                     }
1462 #ifdef ADC_MASTER
1463 			if(jj==0) {
1464 				if(cdsPciModules.pci_rfm_dma[0]) status = rfm55DMAdone(0);
1465 				if(cdsPciModules.pci_rfm_dma[1]) status = rfm55DMAdone(1);
1466 			}
1467 		    // Write GPS time and cycle count as indicator to slave that adc data is ready
1468 	  	    ioMemData->gpsSecond = timeSec;;
1469 		    ioMemData->iodata[jj][ioMemCntr].timeSec = timeSec;;
1470 		    ioMemData->iodata[jj][ioMemCntr].cycle = clock16K;
1471 #endif
1472 
1473 		    // Check for ADC overflows
1474                     for(ii=0;ii<num_outs;ii++)
1475                     {
1476 			if((adcData[jj][ii] > limit) || (adcData[jj][ii] < -limit))
1477 			  {
1478 				overflowAdc[jj][ii] ++;
1479 				overflowAcc ++;
1480 				adcOF[jj] = 1;
1481 			  }
1482                     }
1483 
1484 		   // Clear out last ADC data read for test on next cycle
1485                    packedData = (int *)cdsPciModules.pci_adc[jj];
1486                    *packedData = 0x0;
1487 #if 0
1488 		   // Old support which may or may not come back
1489                    if(cdsPciModules.adcType[jj] == GSC_16AISS8AO4) packedData += 3;
1490                    else if(cdsPciModules.adcType[jj] == GSC_18AISS8AO8) packedData += 3;
1491                    else packedData += 31;
1492 #endif
1493                    packedData += 31;
1494                    *packedData = 0x110000;
1495 		   // Reset DMA Start Flag
1496 		   // This allows ADC to dump next data set whenever it is ready
1497 		   gsaAdcDma2(jj);
1498             }
1499 #endif
1500 
1501 		  // Try synching to 1PPS on ADC[0][31] if not using IRIG-B or TDS
1502 		  // Only try for 1 sec.
1503                   if(!sync21pps)
1504                   {
1505 			// 1PPS signal should rise above 4000 ADC counts if present.
1506                         if((adcData[0][31] < ONE_PPS_THRESH) && (sync21ppsCycles < (CYCLE_PER_SECOND*OVERSAMPLE_TIMES))) 
1507 			{
1508 				ll = -1;
1509 				sync21ppsCycles ++;
1510                         }else {
1511 				// Need to start clocking the DAC outputs.
1512 			        gsaDacTrigger(&cdsPciModules);
1513                                 sync21pps = 1;
1514 				// 1PPS never found, so indicate NO SYNC to user
1515 				if(sync21ppsCycles >= (CYCLE_PER_SECOND*OVERSAMPLE_TIMES))
1516 				{
1517 					syncSource = SYNC_SRC_NONE;
1518 					printf("NO SYNC SOURCE FOUND %d %d\n",sync21ppsCycles,adcData[0][31]);
1519 				} else {
1520 				// 1PPS found and synched to
1521 					printf("GPS Trigg %d %d\n",adcData[0][31],sync21pps);
1522 					syncSource = SYNC_SRC_1PPS;
1523 				}
1524 				pLocalEpics->epicsOutput.timeErr = syncSource;
1525                         }
1526                 }
1527 #ifdef ADC_SLAVE
1528 		// SLAVE gets its adc data from MASTER via ipc shared memory
1529                for(jj=0;jj<cdsPciModules.adcCount;jj++)
1530 		{
1531         		mm = cdsPciModules.adcConfig[jj];
1532                         kk = 0;
1533 		    		rdtscl(cpuClock[8]);
1534                         do{
1535                                 // usleep(1);
1536 		    		rdtscl(cpuClock[9]);
1537 				adcWait = (cpuClock[9] - cpuClock[8])/CPURATE;
1538                                 // kk++;
1539                         }while((ioMemData->iodata[mm][ioMemCntr].cycle != ioClock) && (adcWait < 1000));
1540 			// timeSec = ioMemData->gpsSecond;
1541 	  // printf("cycle = %d  time = %d\n",clock16K,timeSec);
1542 			timeSec = ioMemData->iodata[mm][ioMemCntr].timeSec;
1543                         // }while((ioMemData->iodata[mm][ioMemCntr].cycle != ioClock) && (kk < 1000));
1544 
1545                         if(adcWait >= 1000)
1546                         // if(kk >= 1000)
1547                         {
1548                                 printf ("ADC TIMEOUT %d %d %d %d\n",mm,ioMemData->iodata[mm][ioMemCntr].cycle, ioMemCntr,ioClock);
1549 	  			pLocalEpics->epicsOutput.diagWord |= 0x1;
1550   				return (void *)-1;
1551                         }
1552                         for(ii=0;ii<32;ii++)
1553                         {
1554                                 adcData[jj][ii] = ioMemData->iodata[mm][ioMemCntr].data[ii];
1555                                 dWord[jj][ii] = adcData[jj][ii];
1556 #ifdef OVERSAMPLE
1557 				if (dWordUsed[jj][ii]) {
1558 					dWord[jj][ii] = iir_filter(dWord[jj][ii],FE_OVERSAMPLE_COEFF,2,&dHistory[ii+jj*32][0]);
1559 				}
1560 			if((adcData[jj][ii] > limit) || (adcData[jj][ii] < -limit))
1561 			  {
1562 				overflowAdc[jj][ii] ++;
1563 				overflowAcc ++;
1564 				adcOF[jj] = 1;
1565 			  }
1566 #endif
1567                                 // No filter  dWord[kk][ll] = adcData[kk][ll];
1568                         }
1569                 }
1570 		// Set counters for next read from ipc memory
1571                 ioClock = (ioClock + 1) % 65536;
1572                 ioMemCntr = (ioMemCntr + 1) % IO_MEMORY_SLOTS;
1573         	rdtscl(cpuClock[0]);
1574 
1575 #endif
1576 	}
1577 
1578 	// After first synced ADC read, must set to code to read number samples/cycle
1579         sampleCount = OVERSAMPLE_TIMES;
1580 	}
1581 
1582 #ifdef TEST_SYSTEM
1583         dWord[0][0] = cycleTime;
1584 	dWord[0][1] = usrTime;
1585 	dWord[0][2] = adcHoldTime;
1586 #endif
1587 	// Call the front end specific software ***********************************************
1588         rdtscl(cpuClock[4]);
1589 
1590  	feCode(clock16K,dWord,dacOut,dspPtr[0],&dspCoeff[0],pLocalEpics,0);
1591         rdtscl(cpuClock[5]);
1592 
1593 
1594 // START OF DAC WRITE ***********************************************************************************
1595 #ifdef ADC_MASTER
1596 	   dacBufSelect = (dacBufSelect + 1) % 2;
1597 	   dacBufOffset = dacBufSelect * 0x100;
1598 #endif
1599 	// Write out data to DAC modules
1600 	for(jj=0;jj<cdsPciModules.dacCount;jj++)
1601 	{
1602 #ifdef ADC_SLAVE
1603 	   // SLAVE writes to MASTER via ipc memory
1604 	   mm = cdsPciModules.dacConfig[jj];
1605 // printf("mm = %d\n",mm);
1606 #else
1607 	   // Check Dac output overflow and write to DMA buffer
1608 	   pDacData = (unsigned int *)(cdsPciModules.pci_dac[jj] + dacBufOffset);
1609 #endif
1610 #ifdef ADC_MASTER
1611 	mm = cdsPciModules.dacConfig[jj];
1612 	// if((jj==1) )
1613 	// {
1614 			if(ioMemData->iodata[mm][ioMemCntrDac].cycle == ioClockDac)
1615 			{
1616 				dacEnable |= pBits[jj];
1617 			}else {
1618 				dacEnable &= ~(pBits[jj]);
1619 				dacChanErr[jj] += 1;
1620 			}
1621 	// }
1622 #endif
1623 #ifdef OVERSAMPLE_DAC
1624 	   for (kk=0; kk < OVERSAMPLE_TIMES; kk++) {
1625 #else
1626 		kk = 0;
1627 #endif
1628 		limit = 32000;
1629 		offset = 0; //0x8000;
1630 		mask = 0xffff;
1631 		num_outs = 16;
1632 		if (cdsPciModules.dacType[jj] == GSC_18AISS8AO8) {
1633 			limit *= 4; // 18 bit limit
1634 			offset = 0x20000; // Data coding offset in 18-bit DAC
1635 			mask = 0x3ffff;
1636 			num_outs = 8;
1637 		}
1638 		if (cdsPciModules.dacType[jj] == GSC_18AO8) {
1639 			limit *= 4; // 18 bit limit
1640 			//offset = 0x20000; // Data coding offset in 18-bit DAC
1641 			mask = 0x3ffff;
1642 			num_outs = 8;
1643 
1644 
1645 		}
1646 		if (cdsPciModules.dacType[jj] == GSC_16AISS8AO4) {
1647 		  	num_outs = 4;
1648 		}
1649 		for (ii=0; ii < num_outs; ii++)
1650 		{
1651 #ifdef OVERSAMPLE_DAC
1652 			if (dacOutUsed[jj][ii]) {
1653 #ifdef NO_ZERO_PAD
1654 		 	  dac_in = dacOut[jj][ii];
1655 		 	  dac_in = iir_filter(dac_in,FE_OVERSAMPLE_COEFF,2,&dDacHistory[ii+jj*16][0]);
1656 #else
1657 			  dac_in =  kk == 0? (double)dacOut[jj][ii]: 0.0;
1658 		 	  dac_in = iir_filter(dac_in,FE_OVERSAMPLE_COEFF,2,&dDacHistory[ii+jj*16][0]);
1659 			  dac_in *= OVERSAMPLE_TIMES;
1660 #endif
1661 			}
1662 			else dac_in = 0.0;
1663 			// Smooth out some of the double > short roundoff errors
1664 			if(dac_in > 0.0) dac_in += 0.5;
1665 			else dac_in -= 0.5;
1666 			dac_out = dac_in;
1667 #else
1668 #ifdef ADC_MASTER
1669 			if(!dacChanErr[jj]) {
1670 				dac_out = ioMemData->iodata[mm][ioMemCntrDac].data[ii];
1671 				// Zero out data in case user app dies by next cycle
1672 				// when two or more apps share same DAC module.
1673 				ioMemData->iodata[mm][ioMemCntrDac].data[ii] = 0;
1674 			} else dac_out = 0;
1675 #else
1676 			dac_out = dacOut[jj][ii];
1677 #endif
1678 #endif
1679 			if(dac_out > limit) 
1680 			{
1681 				dac_out = limit;
1682 				overflowDac[jj][ii] ++;
1683 				overflowAcc ++;
1684 				dacOF[jj] = 1;
1685 			}
1686 			if(dac_out < -limit) 
1687 			{
1688 				dac_out = -limit;
1689 				overflowDac[jj][ii] ++;
1690 				overflowAcc ++;
1691 				dacOF[jj] = 1;
1692 			}
1693 			// Load last values to EPICS channels for monitoring on GDS_TP screen.
1694 		 	dacOutEpics[jj][ii] = dac_out;
1695 
1696 			// Load DAC testpoints
1697 			floatDacOut[16*jj + ii] = dac_out;
1698 #ifdef ADC_SLAVE
1699 			memCtr = (ioMemCntrDac + kk) % IO_MEMORY_SLOTS;
1700 			// Only write to DAC channels being used to allow two or more
1701 			// slaves to write to same DAC module.
1702 			if (dacOutUsed[jj][ii]) 
1703 	   			ioMemData->iodata[mm][memCtr].data[ii] = dac_out;
1704 #else
1705 			dac_out += offset;
1706 			// if (ii == 15) { dac_out = dWord[0][31]; }
1707 			*pDacData =  (unsigned int)(dac_out & mask);
1708 			pDacData ++;
1709 #endif
1710 		}
1711 #ifdef ADC_SLAVE
1712 		// Write cycle count to make DAC data complete
1713 		ioMemData->iodata[mm][memCtr].cycle = (ioClockDac + kk) % 65536;
1714 #endif
1715 #ifdef OVERSAMPLE_DAC
1716   	   }
1717 #endif
1718 #ifdef ADC_MASTER
1719 		// Mark cycle count as having been used -1
1720 		// Forces slaves to mark this cycle or will not be used again by Master
1721 		ioMemData->iodata[mm][ioMemCntrDac].cycle = -1;
1722 #endif
1723 	}
1724 
1725 
1726 #ifdef ADC_SLAVE
1727 		// Increment DAC memory block pointers for next cycle
1728 		ioClockDac = (ioClockDac + OVERSAMPLE_TIMES) % 65536;
1729 		ioMemCntrDac = (ioMemCntrDac  + OVERSAMPLE_TIMES) % IO_MEMORY_SLOTS;
1730 #endif
1731 #ifdef ADC_MASTER
1732 		// Increment DAC memory block pointers for next cycle
1733 		ioClockDac = (ioClockDac + 1) % 65536;
1734 		ioMemCntrDac = (ioMemCntrDac + 1) % IO_MEMORY_SLOTS;
1735 #endif
1736 	if(dacWriteEnable < 10) dacWriteEnable ++;
1737 // END OF DAC WRITE ***********************************************************************************
1738 // BEGIN HOUSEKEEPING *********************************************************************************
1739 
1740 #ifdef ADC_MASTER
1741         if(clock16K == 0)
1742         {
1743 		if(cdsPciModules.gpsType == SYMCOM_RCVR) 
1744 		{
1745 		// Retrieve time set in at adc read and report offset from 1PPS
1746 			gps_receiver_locked = getGpsTime(&timeSec,&usec);
1747 			pLocalEpics->epicsOutput.diags[FE_DIAGS_IRIGB_TIME] = usec;
1748 		}
1749                 duotoneMean = duotoneTotal/CYCLE_PER_SECOND;
1750                 duotoneTotal = 0.0;
1751                 // duotoneMeanDac = duotoneTotalDac/CYCLE_PER_SECOND;
1752                 // duotoneTotalDac = 0.0;
1753         }
1754         duotoneDac[(clock16K + 6) % CYCLE_PER_SECOND] = dWord[0][15];
1755         duotoneTotalDac += dWord[0][15];
1756         duotone[(clock16K + 6) % CYCLE_PER_SECOND] = dWord[0][31];
1757         duotoneTotal += dWord[0][31];
1758         if(clock16K == 16)
1759         {
1760                 duotoneTime = duotime(12, duotoneMean, duotone);
1761                 pLocalEpics->epicsOutput.diags[FE_DIAGS_DUOTONE_TIME] = duotoneTime;
1762 		if((usec > 20) || (usec < 5)) diagWord |= 0x10;;
1763 		// duotoneTimeDac = duotime(12, duotoneMeanDac, duotoneDac);
1764                 // pLocalEpics->epicsOutput.diags[5] = duotoneTimeDac;
1765 		// printf("du = %f %f %f %f %f\n",duotone[5], duotone[6], duotone[7],duotone[8],duotone[9]);
1766         }
1767 #endif
1768 
1769 
1770 	// Send timing info to EPICS at 1Hz
1771         if((subcycle == 0) && (daqCycle == 15))
1772         {
1773 	  pLocalEpics->epicsOutput.cpuMeter = timeHold;
1774 	  pLocalEpics->epicsOutput.cpuMeterMax = timeHoldMax;
1775 #ifdef ADC_MASTER
1776   	  pLocalEpics->epicsOutput.diags[FE_DIAGS_DAC_MASTER_STAT] = dacEnable;
1777 #endif
1778           timeHold = 0;
1779 	  if (timeSec % 4 == 0) pLocalEpics->epicsOutput.adcWaitTime = adcHoldTimeMin;
1780 	  else if (timeSec % 4 == 1)
1781 		pLocalEpics->epicsOutput.adcWaitTime =  adcHoldTimeMax;
1782 	  else
1783 	  	pLocalEpics->epicsOutput.adcWaitTime = adcHoldTimeAvg/CYCLE_PER_SECOND;
1784 	  adcHoldTimeAvgPerSec = adcHoldTimeAvg/CYCLE_PER_SECOND;
1785 	  adcHoldTimeMax = 0;
1786 	  adcHoldTimeMin = 0xffff;
1787 	  adcHoldTimeAvg = 0;
1788 	  if((adcHoldTime > CYCLE_TIME_ALRM_HI) || (adcHoldTime < CYCLE_TIME_ALRM_LO)) diagWord |= FE_ADC_HOLD_ERR;
1789 	  if(timeHoldMax > CYCLE_TIME_ALRM) diagWord |= FE_PROC_TIME_ERR;
1790   	  if(pLocalEpics->epicsInput.diagReset || initialDiagReset)
1791 	  {
1792 		initialDiagReset = 0;
1793 		pLocalEpics->epicsInput.diagReset = 0;
1794   		// pLocalEpics->epicsOutput.diags[1] = 0;
1795 		timeHoldMax = 0;
1796 	  	diagWord = 0;
1797 		ipcErrBits = 0;
1798 #ifndef NO_RTL
1799 		// printf("DIAG RESET\n");
1800 #endif
1801 	  }
1802 	  // Flip the onePPS various once/sec as a watchdog monitor.
1803 	  // pLocalEpics->epicsOutput.onePps ^= 1;
1804 	  pLocalEpics->epicsOutput.diagWord = diagWord;
1805         }
1806 
1807 	/* Update User code Epics variables */
1808 #if MAX_MODULES > END_OF_DAQ_BLOCK
1809 	epicsCycle = (epicsCycle + 1) % (MAX_MODULES + 2);
1810 #else
1811 	epicsCycle = subcycle;
1812 #endif
1813 
1814   	for (system = 0; system < NUM_SYSTEMS; system++)
1815 		updateEpics(epicsCycle, dspPtr[system], pDsp[system],
1816 			    &dspCoeff[system], pCoeff[system]);
1817 
1818 	// Check if user has pushed reset button.
1819 	// If so, kill the task
1820         vmeDone = stop_working_threads | checkEpicsReset(epicsCycle, pLocalEpics);
1821 	// usleep(1);
1822 
1823   
1824 	// If synced to 1PPS on startup, continue to check that code
1825 	// is still in sync with 1PPS.
1826 	if(syncSource == SYNC_SRC_1PPS)
1827 	{
1828 
1829 		// Assign chan 32 to onePps 
1830 		onePps = adcData[0][31];
1831 		if((onePps > ONE_PPS_THRESH) && (onePpsHi == 0))  
1832 		{
1833 			onePpsTime = clock16K;
1834 			onePpsHi = 1;
1835 		}
1836 		if(onePps < ONE_PPS_THRESH) onePpsHi = 0;  
1837 
1838 		// Check if front end continues to be in sync with 1pps
1839 		// If not, set sync error flag
1840 		if(onePpsTime > 1) pLocalEpics->epicsOutput.timeErr |= TIME_ERR_1PPS;
1841 	}
1842 
1843 #ifndef ADC_MASTER
1844  // Read Dio cards once per second
1845         if(clock16K < cdsPciModules.doCount)
1846         {
1847                 kk = clock16K;
1848                 ii = cdsPciModules.doInstance[kk];
1849                 if(cdsPciModules.doType[kk] == ACS_8DIO)
1850                 {
1851 	  		if (rioReadOps[ii] & 1) rioInputInput[ii] = readIiroDio(&cdsPciModules, kk) & 0xff;
1852 	  		if (rioReadOps[ii] & 2) rioInputOutput[ii] = readIiroDioOutput(&cdsPciModules, kk) & 0xff;
1853                 }
1854                 if(cdsPciModules.doType[kk] == ACS_16DIO)
1855                 {
1856                         rioInput1[ii] = readIiroDio1(&cdsPciModules, kk) & 0xffff;
1857                 }
1858 		if(cdsPciModules.doType[kk] == ACS_24DIO)
1859 		{
1860 		  dioInput[ii] = readDio(&cdsPciModules, kk);
1861 		}
1862 		if (cdsPciModules.doType[kk] == CON_6464DIO) {
1863 	 		CDIO6464InputInput[ii] = readInputCDIO6464l(&cdsPciModules, kk);
1864 		}
1865         }
1866         // Write Dio cards on change
1867         for(kk=0;kk < cdsPciModules.doCount;kk++)
1868         {
1869                 ii = cdsPciModules.doInstance[kk];
1870                 if((cdsPciModules.doType[kk] == ACS_8DIO) && (rioOutput[ii] != rioOutputHold[ii]))
1871                 {
1872                         writeIiroDio(&cdsPciModules, kk, rioOutput[ii]);
1873                         rioOutputHold[ii] = rioOutput[ii];
1874                 } else 
1875                 if((cdsPciModules.doType[kk] == ACS_16DIO) && (rioOutput1[ii] != rioOutputHold1[ii]))
1876                 {
1877                         writeIiroDio1(&cdsPciModules, kk, rioOutput1[ii]);
1878                         rioOutputHold1[ii] = rioOutput1[ii];
1879                         // printf("write relay mod %d = %d\n",kk,rioOutput1[ii]);
1880                 } else 
1881                 if(cdsPciModules.doType[kk] == CON_32DO)
1882                 {
1883                         if (CDO32Input[ii] != CDO32Output[ii]) {
1884                           CDO32Input[ii] = writeCDO32l(&cdsPciModules, kk, CDO32Output[ii]);
1885                         }
1886 		} else if (cdsPciModules.doType[kk] == CON_1616DIO) {
1887 #if 0
1888 			if (CDIO1616Input[ii] != CDIO1616Output[ii]) {
1889 			  CDIO1616Input[ii] = writeCDIO1616l(&cdsPciModules, kk, CDIO1616Output[ii]);
1890 			}
1891 #endif
1892 			CDIO1616InputInput[ii] = readInputCDIO1616l(&cdsPciModules, kk);
1893 		} else if (cdsPciModules.doType[kk] == CON_6464DIO) {
1894 			if (CDIO6464Input[ii] != CDIO6464Output[ii]) {
1895 			  CDIO6464Input[ii] = writeCDIO6464l(&cdsPciModules, kk, CDIO6464Output[ii]);
1896 			}
1897                 } else
1898                 if((cdsPciModules.doType[kk] == ACS_24DIO) && (dioOutputHold[ii] != dioOutput[ii]))
1899 		{
1900                         writeDio(&cdsPciModules, kk, dioOutput[ii]);
1901 			dioOutputHold[ii] = dioOutput[ii];
1902 		}
1903         }
1904 
1905 #endif
1906 
1907 #ifndef NO_DAQ
1908 		
1909 		// Call daqLib
1910 		if (cycle_gps_time == 0) startGpsTime = timeSec;
1911 		cycle_gps_time = timeSec; // Time at which ADCs triggered
1912 		pLocalEpics->epicsOutput.diags[FE_DIAGS_DAQ_BYTE_CNT] = 
1913 			daqWrite(1,dcuId,daq,DAQ_RATE,testpoint,dspPtr[0],myGmError2,pLocalEpics->epicsOutput.gdsMon,xExc);
1914 #endif
1915 
1916 #ifdef NO_RTL
1917 	//rt_sleep(nano2count(2000));
1918 	//msleep(1);
1919 #else
1920 	// usleep(1);
1921 #endif
1922 
1923         if((subcycle == 0) && (daqCycle == 14))
1924         {
1925 	  pLocalEpics->epicsOutput.diags[FE_DIAGS_USER_TIME] = usrHoldTime;
1926 	  pLocalEpics->epicsOutput.diags[FE_DIAGS_IPC_STAT] = ipcErrBits;
1927 	  // Create FB status word for return to EPICS
1928 #ifdef USE_GM
1929   	  pLocalEpics->epicsOutput.diags[FE_DIAGS_FB_NET_STAT] = (fbStat[1] & 3) * 4 + (fbStat[0] & 3);
1930 #endif
1931 #if defined(SHMEM_DAQ)
1932 	  mxStat = 0;
1933 	  mxDiagR = daqPtr->status;
1934 	  if((mxDiag & 1) != (mxDiagR & 1)) mxStat = 1;
1935 	  if((mxDiag & 2) != (mxDiagR & 2)) mxStat += 2;
1936 	  pLocalEpics->epicsOutput.diags[FE_DIAGS_FB_NET_STAT] = mxStat;
1937   	  mxDiag = mxDiagR;
1938 #endif
1939 	  usrHoldTime = 0;
1940   	  if((pLocalEpics->epicsInput.overflowReset) || (overflowAcc > 0x1000000))
1941 	  {
1942 
1943 #ifdef ROLLING_OVERFLOWS
1944                 if (pLocalEpics->epicsInput.overflowReset) {
1945                    for (ii = 0; ii < 16; ii++) {
1946                       for (jj = 0; jj < cdsPciModules.adcCount; jj++) {
1947                          overflowAdc[jj][ii] = 0;
1948                          overflowAdc[jj][ii + 16] = 0;
1949                       }
1950 
1951                       for (jj = 0; jj < cdsPciModules.dacCount; jj++) {
1952                          overflowDac[jj][ii] = 0;
1953                       }
1954                    }
1955                 }
1956 #endif
1957 
1958 		pLocalEpics->epicsInput.overflowReset = 0;
1959 		pLocalEpics->epicsOutput.ovAccum = 0;
1960 		overflowAcc = 0;
1961 	  }
1962         }
1963 
1964 #ifdef ADC_SLAVE
1965         if(clock16K == 1)
1966 	{
1967           pLocalEpics->epicsOutput.timeDiag = timeSec;
1968 	}
1969 #endif
1970         if(clock16K == 220)
1971 	{
1972 	      // Send DAC output values at 16Hzfb
1973 	      for(jj=0;jj<cdsPciModules.dacCount;jj++)
1974 	      {
1975 	    	for(ii=0;ii<16;ii++)
1976 	    	{
1977 			pLocalEpics->epicsOutput.dacValue[jj][ii] = dacOutEpics[jj][ii];
1978 		}
1979 	      }
1980 	}
1981 
1982         if(clock16K == 200)
1983         {
1984 		pLocalEpics->epicsOutput.ovAccum = overflowAcc;
1985 	  for(jj=0;jj<cdsPciModules.adcCount;jj++)
1986 	  {
1987 	    // SET/CLR Channel Hopping Error
1988 	    if(adcChanErr[jj]) pLocalEpics->epicsOutput.statAdc[jj] &= ~(2);
1989  	    else pLocalEpics->epicsOutput.statAdc[jj] |= 2;
1990 	    adcChanErr[jj] = 0;
1991 	    // SET/CLR Overflow Error
1992 	    if(adcOF[jj]) pLocalEpics->epicsOutput.statAdc[jj] &= ~(4);
1993  	    else pLocalEpics->epicsOutput.statAdc[jj] |= 4;
1994 	    adcOF[jj] = 0;
1995 	    for(ii=0;ii<32;ii++)
1996 	    {
1997 		pLocalEpics->epicsOutput.overflowAdc[jj][ii] = overflowAdc[jj][ii];
1998 
1999 #ifdef ROLLING_OVERFLOWS
2000                 if (overflowAdc[jj][ii] > 0x1000000) {
2001 		   overflowAdc[jj][ii] = 0;
2002                 }
2003 #else
2004 		overflowAdc[jj][ii] = 0;
2005 #endif
2006 
2007 	    }
2008 	  }
2009 	  for(jj=0;jj<cdsPciModules.dacCount;jj++)
2010 	  {
2011 	    if(dacOF[jj]) pLocalEpics->epicsOutput.statDac[jj] &= ~(4);
2012  	    else pLocalEpics->epicsOutput.statDac[jj] |= 4;
2013 	    dacOF[jj] = 0;
2014 	    if(dacChanErr[jj]) pLocalEpics->epicsOutput.statDac[jj] &= ~(2);
2015  	    else pLocalEpics->epicsOutput.statDac[jj] |= 2;
2016 	    dacChanErr[jj] = 0;
2017 	    for(ii=0;ii<16;ii++)
2018 	    {
2019 		pLocalEpics->epicsOutput.overflowDac[jj][ii] = overflowDac[jj][ii];
2020 
2021 #ifdef ROLLING_OVERFLOWS
2022                 if (overflowDac[jj][ii] > 0x1000000) {
2023 		   overflowDac[jj][ii] = 0;
2024                 }
2025 #else
2026 		overflowDac[jj][ii] = 0;
2027 #endif
2028 
2029 	    }
2030 	  }
2031         }
2032 #ifdef ADC_MASTER
2033  	static const own_data_base_cycle = 300;
2034 	// Deal with the own-data bits on the VMIC 5565 rfm cards
2035 	if (cdsPciModules.rfmCount > 0) {
2036         	if (clock16K >= own_data_base_cycle && clock16K < (own_data_base_cycle + cdsPciModules.rfmCount)) {
2037 			int mod = clock16K - own_data_base_cycle;
2038 			if (cdsPciModules.rfmType[mod] == 0x5565) {
2039 				// Check the own-data light
2040 				if ((cdsPciModules.rfm_reg[mod]->LCSR1 & 1) == 0) ipcErrBits |= 8;
2041 				//printk("RFM %d own data %d\n", mod, cdsPciModules.rfm_reg[mod]->LCSR1);
2042 			}
2043 		}
2044 		if (clock16K >= (own_data_base_cycle + cdsPciModules.rfmCount) && clock16K < (own_data_base_cycle + cdsPciModules.rfmCount*2)) {
2045 			int mod = clock16K - own_data_base_cycle - cdsPciModules.rfmCount;
2046 			if (cdsPciModules.rfmType[mod] == 0x5565) {
2047 				// Reset the own-data light
2048 				cdsPciModules.rfm_reg[mod]->LCSR1 &= ~1;
2049 			}
2050 		}
2051 		if (clock16K >= (own_data_base_cycle + 2*cdsPciModules.rfmCount) && clock16K < (own_data_base_cycle + cdsPciModules.rfmCount*3)) {
2052 			int mod = clock16K - own_data_base_cycle - cdsPciModules.rfmCount*2;
2053 			if (cdsPciModules.rfmType[mod] == 0x5565) {
2054 				// Write data out to the RFM to trigger the light
2055 	  			((volatile long *)(cdsPciModules.pci_rfm[mod]))[2] = 0;
2056 			}
2057 		}
2058 	}
2059 // DAC WD Write for 18 bit DAC modules
2060 // Check once per second on code cycle 400 to dac count
2061 // Only one write per code cycle to reduce time
2062        	if (clock16K >= 400 && clock16K < (400 + cdsPciModules.dacCount)) 
2063 	{
2064 		jj = clock16K - 400;
2065 		if(cdsPciModules.dacType[jj] == GSC_18AO8)
2066 		{
2067 			static int dacWatchDog = 0;
2068 			if (clock16K == 400) dacWatchDog ^= 1;
2069 			volatile GSA_18BIT_DAC_REG *dac18bitPtr = dacPtr[jj];
2070 			dac18bitPtr->digital_io_ports = (dacWatchDog | GSAO_18BIT_DIO_RW);
2071 			//out_buf_size = dac18bitPtr->OUT_BUF_SIZE;
2072 			//printf("Out buffg size %d = %d\n",jj,out_buf_size);
2073 
2074 		}
2075 	}
2076 // AI Chassis WD CHECK for 18 bit DAC modules
2077 // Check once per second on code cycle 500 to dac count
2078 // Only one read per code cycle to reduce time
2079        	if (clock16K >= 500 && clock16K < (500 + cdsPciModules.dacCount)) 
2080 	{
2081 		jj = clock16K - 500;
2082 		if(cdsPciModules.dacType[jj] == GSC_18AO8)
2083 		{
2084 			static int dacWDread = 0;
2085 			volatile GSA_18BIT_DAC_REG *dac18bitPtr = dacPtr[jj];
2086 			dacWDread = dac18bitPtr->digital_io_ports;
2087 			if(((dacWDread >> 8) & 1) > 0)
2088 			    pLocalEpics->epicsOutput.statDac[jj] &= ~(16);
2089 			    else pLocalEpics->epicsOutput.statDac[jj] |= 16;
2090 
2091 		}
2092 	}
2093 
2094 // 18bit FIFO size check, once per second
2095 // Used to verify DAC is clocking correctly and code is transmitting data on time.
2096 	// Uncomment to read 18-bit DAC buffer size
2097 	//extern volatile GSA_DAC_REG *dacPtr[MAX_DAC_MODULES];
2098         //volatile GSA_18BIT_DAC_REG *dac18bitPtr = dacPtr[0];
2099         //out_buf_size = dac18bitPtr->OUT_BUF_SIZE;
2100        	if (clock16K >= 600 && clock16K < (600 + cdsPciModules.dacCount)) 
2101 	{
2102 		jj = clock16K - 600;
2103 		if(cdsPciModules.dacType[jj] == GSC_18AO8)
2104 		{
2105 			volatile GSA_18BIT_DAC_REG *dac18bitPtr = dacPtr[jj];
2106 			out_buf_size = dac18bitPtr->OUT_BUF_SIZE;
2107 			if(out_buf_size > 8)
2108 			    pLocalEpics->epicsOutput.statDac[jj] &= ~(8);
2109 			    else pLocalEpics->epicsOutput.statDac[jj] |= 8;
2110 
2111 		}
2112 		if(cdsPciModules.dacType[jj] == GSC_16AO16)
2113 		{
2114 			status = checkDacBuffer(jj);
2115 			if(status != 3)
2116 			    pLocalEpics->epicsOutput.statDac[jj] &= ~(8);
2117 			    else pLocalEpics->epicsOutput.statDac[jj] |= 8;
2118 		}
2119 	}
2120 
2121 #endif
2122 	// Measure time to complete 1 cycle
2123         rdtscl(cpuClock[1]);
2124 
2125 	// Compute max time of one cycle.
2126 	cycleTime = (cpuClock[1] - cpuClock[0])/CPURATE;
2127 	if (longestWrite2 < ((tempClock[3]-tempClock[2])/CPURATE)) longestWrite2 = (tempClock[3]-tempClock[2])/CPURATE;
2128 	if (cycleTime > (1000000/CYCLE_PER_SECOND))  {
2129 		printf("cycle %d time %d; adcWait %d; write1 %d; write2 %d; longest write2 %d\n", clock16K, cycleTime, adcWait, (tempClock[1]-tempClock[0])/CPURATE, (tempClock[3]-tempClock[2])/CPURATE, longestWrite2);
2130 	}
2131 	// Hold the max cycle time over the last 1 second
2132 	if(cycleTime > timeHold) timeHold = cycleTime;
2133 	// Hold the max cycle time since last diag reset
2134 	if(cycleTime > timeHoldMax) timeHoldMax = cycleTime;
2135 	adcHoldTime = (cpuClock[0] - adcTime)/CPURATE;
2136 	if(adcHoldTime > adcHoldTimeMax) adcHoldTimeMax = adcHoldTime;
2137 	if(adcHoldTime < adcHoldTimeMin) adcHoldTimeMin = adcHoldTime;
2138 	adcHoldTimeAvg += adcHoldTime;
2139 	if (adcHoldTimeMax > adcHoldTimeEverMax)  {
2140 		adcHoldTimeEverMax = adcHoldTimeMax;
2141 		adcHoldTimeEverMaxWhen = cycle_gps_time;
2142 	}
2143 	adcTime = cpuClock[0];
2144 	// Calc the max time of one cycle of the user code
2145 #ifdef ADC_MASTER
2146 	usrTime = (cpuClock[4] - cpuClock[0])/CPURATE;
2147 #else
2148 	usrTime = (cpuClock[5] - cpuClock[4])/CPURATE;
2149 #endif
2150 	if(usrTime > usrHoldTime) usrHoldTime = usrTime;
2151 
2152         // Update internal cycle counters
2153           clock16K += 1;
2154           clock16K %= CYCLE_PER_SECOND;
2155 	  clock1Min += 1;
2156 	  clock1Min %= CYCLE_PER_MINUTE;
2157           if(subcycle == DAQ_CYCLE_CHANGE) daqCycle = (daqCycle + 1) % 16;
2158           if(subcycle == END_OF_DAQ_BLOCK) /*we have reached the 16Hz second barrier*/
2159             {
2160               /* Reset the data cycle counter */
2161               subcycle = 0;
2162   
2163             }
2164           else{
2165             /* Increment the internal cycle counter */
2166             subcycle ++;                                                
2167           }
2168 
2169   }
2170 
2171   printf("exiting from fe_code()\n");
2172   pLocalEpics->epicsOutput.cpuMeter = 0;
2173 
2174   /* System reset command received */
2175   return (void *)-1;
2176 }
2177 // MAIN routine: Code starting point ****************************************************************
2178 #ifdef NO_RTL
2179 
2180 // These externs and "16" need to go to a header file (mbuf.h)
2181 extern void *kmalloc_area[16];
2182 extern int mbuf_allocate_area(char *name, int size, struct file *file);
2183 
2184 // /proc filesystem entry
2185 struct proc_dir_entry *proc_entry;
2186 
2187 int
2188 procfile_read(char *buffer,
2189 	      char **buffer_location,
2190 	      off_t offset, int buffer_length, int *eof, void *data)
2191 {
2192 	int ret;
2193 	
2194 	/* 
2195 	 * We give all of our information in one go, so if the
2196 	 * user asks us if we have more information the
2197 	 * answer should always be no.
2198 	 *
2199 	 * This is important because the standard read
2200 	 * function from the library would continue to issue
2201 	 * the read system call until the kernel replies
2202 	 * that it has no more information, or until its
2203 	 * buffer is filled.
2204 	 */
2205 	if (offset > 0) {
2206 		/* we have finished to read, return 0 */
2207 		ret  = 0;
2208 	} else {
2209 		/* fill the buffer, return the buffer size */
2210 		ret = sprintf(buffer,
2211 
2212 			"startGpsTime=%d\n"
2213 			"uptime=%d\n"
2214 			"adcHoldTime=%d\n"
2215 			"adcHoldTimeEverMax=%d\n"
2216 			"adcHoldTimeEverMaxWhen=%d\n"
2217 			"adcHoldTimeMax=%d\n"
2218 			"adcHoldTimeMin=%d\n"
2219 			"adcHoldTimeAvg=%d\n"
2220 			"usrTime=%d\n"
2221 			"usrHoldTime=%d\n"
2222 			"cycle=%d\n"
2223 			"gps=%d\n"
2224 			"buildDate=%s\n",
2225 
2226 			startGpsTime,
2227 			cycle_gps_time - startGpsTime,
2228 			adcHoldTime,
2229 			adcHoldTimeEverMax,
2230 			adcHoldTimeEverMaxWhen,
2231 			adcHoldTimeMax,
2232 			adcHoldTimeMin,
2233 			adcHoldTimeAvgPerSec,
2234 			usrTime,
2235 			usrHoldTime,
2236 			clock16K,
2237 			cycle_gps_time,
2238 			build_date);
2239 	}
2240 
2241 	return ret;
2242 }
2243 
2244 /* Track dependency between the IOP and the slaves */
2245 #ifdef ADC_MASTER
2246 int need_to_load_IOP_first;
2247 EXPORT_SYMBOL(need_to_load_IOP_first);
2248 #endif
2249 #ifdef ADC_SLAVE
2250 extern int need_to_load_IOP_first;
2251 #endif
2252 
2253 
2254 int init_module (void)
2255 #else
2256 int main(int argc, char **argv)
2257 #endif
2258 {
2259 #ifndef NO_RTL
2260         pthread_attr_t attr;
2261 #endif
2262  	int status;
2263 	int ii,jj,kk;
2264 	char fname[128];
2265 	int cards;
2266 	int adcCnt;
2267 	int dacCnt;
2268 	int doCnt;
2269 	int do32Cnt;
2270 	int doIIRO16Cnt;
2271 
2272 #ifdef ADC_SLAVE
2273 	need_to_load_IOP_first = 0;
2274 #endif
2275 
2276 #ifdef DOLPHIN_TEST
2277 #ifdef X1X14_CODE
2278 	static const target_node = 8; //DIS_TARGET_NODE;
2279 #else
2280 	static const target_node = 12; //DIS_TARGET_NODE;
2281 #endif
2282 	status = init_dolphin(target_node);
2283 	if (status != 0) {
2284 		return -1;
2285 	}
2286 #endif
2287 
2288 	proc_entry = create_proc_entry(SYSTEM_NAME_STRING_LOWER, 0644, NULL);
2289 	
2290 	if (proc_entry == NULL) {
2291 		remove_proc_entry(SYSTEM_NAME_STRING_LOWER, NULL);
2292 		printk(KERN_ALERT "Error: Could not initialize /proc/%s\n",
2293 		       SYSTEM_NAME_STRING_LOWER);
2294 		return -ENOMEM;
2295 	}
2296 	
2297 	proc_entry->read_proc = procfile_read;
2298 	//proc_entry->owner 	 = THIS_MODULE;
2299 	proc_entry->mode 	 = S_IFREG | S_IRUGO;
2300 	proc_entry->uid 	 = 0;
2301 	proc_entry->gid 	 = 0;
2302 	proc_entry->size 	 = 10240;
2303 
2304 	printf("startup time is %ld\n", current_time());
2305 	jj = 0;
2306 	printf("cpu clock %u\n",cpu_khz);
2307 
2308 #ifdef NO_RTL
2309 
2310         int ret =  mbuf_allocate_area(SYSTEM_NAME_STRING_LOWER, 64*1024*1024, 0);
2311         if (ret < 0) {
2312                 printf("mbuf_allocate_area() failed; ret = %d\n", ret);
2313                 return -1;
2314         }
2315         _epics_shm = (unsigned char *)(kmalloc_area[ret]);
2316         printf("Epics shmem set at 0x%p\n", _epics_shm);
2317         ret =  mbuf_allocate_area("ipc", 4*1024*1024, 0);
2318         if (ret < 0) {
2319                 printf("mbuf_allocate_area(ipc) failed; ret = %d\n", ret);
2320                 return -1;
2321         }
2322         _ipc_shm = (unsigned char *)(kmalloc_area[ret]);
2323 
2324 #else
2325         /*
2326          * Create the shared memory area.  By passing a non-zero value
2327          * for the mode, this means we also create a node in the GPOS.
2328          */       
2329 
2330 	/* See if we can open new-style shared memory file */
2331 	sprintf(fname, "/rtl_mem_%s", SYSTEM_NAME_STRING_LOWER);
2332         wfd = shm_open(fname, RTL_O_RDWR, 0666);
2333 	if (wfd == -1) {
2334           printf("Warning, couldn't open `%s' read/write (errno=%d)\n", fname, errno);
2335           wfd = shm_open("/rtl_epics", RTL_O_RDWR, 0666);
2336           if (wfd == -1) {
2337                 printf("open failed for write on /rtl_epics (%d)\n",errno);
2338                 rtl_perror("shm_open()");
2339                 return -1;
2340           }
2341 	}
2342 
2343 	// Set pointer to EPICS shared memory
2344         _epics_shm = (unsigned char *)rtl_mmap(NULL,MMAP_SIZE,PROT_READ|PROT_WRITE,MAP_SHARED,wfd,0);
2345         if (_epics_shm == MAP_FAILED) {
2346                 printf("mmap failed for epics shared memory area\n");
2347                 rtl_perror("mmap()");
2348                 return -1;
2349         }
2350 
2351 	// See if IPC area is available, open and map it
2352 	// IPC area is used to pass data between realtime processes on different cores.
2353 	strcpy(fname, "/rtl_mem_ipc");
2354         ipc_fd = shm_open(fname, RTL_O_RDWR, 0666);
2355 	if (ipc_fd == -1) {
2356           //printf("Warning, couldn't open `%s' read/write (errno=%d)\n", fname, errno);
2357 	} else {
2358           _ipc_shm = (unsigned char *)rtl_mmap(NULL,MMAP_SIZE,PROT_READ|PROT_WRITE,MAP_SHARED,ipc_fd,0);
2359           if (_ipc_shm == MAP_FAILED) {
2360                 printf("mmap failed for IPC shared memory area\n");
2361                 rtl_perror("mmap()");
2362                 return -1;
2363 	  }
2364         }
2365 #endif
2366 	printf("IPC at 0x%p\n",_ipc_shm);
2367   	ioMemData = (IO_MEM_DATA *)(_ipc_shm+ 0x4000);
2368 
2369 
2370 // If DAQ is via shared memory (Framebuilder code running on same machine or MX networking is used)
2371 // attach DAQ shared memory location.
2372 #if defined(SHMEM_DAQ)
2373 #ifdef NO_RTL
2374         sprintf(fname, "%s_daq", SYSTEM_NAME_STRING_LOWER);
2375         ret =  mbuf_allocate_area(fname, 64*1024*1024, 0);
2376         if (ret < 0) {
2377                 printf("mbuf_allocate_area() failed; ret = %d\n", ret);
2378                 return -1;
2379         }
2380         _daq_shm = (unsigned char *)(kmalloc_area[ret]);
2381         printf("Allocated daq shmem; set at 0x%p\n", _daq_shm);
2382  	daqPtr = (struct rmIpcStr *) _daq_shm;
2383 #else
2384 	// See if frame builder DAQ comm area available
2385 	sprintf(fname, "/rtl_mem_%s_daq", SYSTEM_NAME_STRING_LOWER);
2386         daq_fd = shm_open(fname, RTL_O_RDWR, 0666);
2387 	if (daq_fd == -1) {
2388           printf("Error: couldn't open `%s' read/write (errno=%d)\n", fname, errno);
2389 	  return -1;
2390 	} else {
2391           _daq_shm = (unsigned char *)rtl_mmap(NULL,MMAP_SIZE,PROT_READ|PROT_WRITE,MAP_SHARED,daq_fd,0);
2392           if (_daq_shm == MAP_FAILED) {
2393                 printf("mmap failed for DAQ shared memory area\n");
2394                 rtl_perror("mmap()");
2395                 return -1;
2396 	  }
2397  	  daqPtr = (struct rmIpcStr *) _daq_shm;
2398         }
2399 #endif
2400 #endif
2401 
2402 	// Find and initialize all PCI I/O modules *******************************************************
2403 	  // Following I/O card info is from feCode
2404 	  cards = sizeof(cards_used)/sizeof(cards_used[0]);
2405 	  printf("configured to use %d cards\n", cards);
2406 	  cdsPciModules.cards = cards;
2407 	  cdsPciModules.cards_used = cards_used;
2408           //return -1;
2409 	printf("Initializing PCI Modules\n");
2410 	cdsPciModules.adcCount = 0;
2411 	cdsPciModules.dacCount = 0;
2412 	cdsPciModules.dioCount = 0;
2413 	cdsPciModules.doCount = 0;
2414 
2415 #ifndef ADC_SLAVE
2416 	// Call PCI initialization routine in map.c file.
2417 	status = mapPciModules(&cdsPciModules);
2418 	// return 0;
2419 #endif
2420 #ifdef ADC_SLAVE
2421 // If running as a slave process, I/O card information is via ipc shared memory
2422 	printf("%d PCI cards found\n",ioMemData->totalCards);
2423 	status = 0;
2424 	adcCnt = 0;
2425 	dacCnt = 0;
2426 	doCnt = 0;
2427 	do32Cnt = 0;
2428 	doIIRO16Cnt = 0;
2429 
2430 	// Have to search thru all cards and find desired instance for application
2431 	// Master will map ADC cards first, then DAC and finally DIO
2432 	for(ii=0;ii<ioMemData->totalCards;ii++)
2433 	{
2434 		printf("Model %d = %d\n",ii,ioMemData->model[ii]);
2435 		for(jj=0;jj<cards;jj++)
2436 		{
2437 		   switch(ioMemData->model[ii])
2438 		   {
2439 			case GSC_16AI64SSA:
2440 				if((cdsPciModules.cards_used[jj].type == GSC_16AI64SSA) && 
2441 					(cdsPciModules.cards_used[jj].instance == adcCnt))
2442 				{
2443 					printf("Found ADC at %d %d\n",jj,ioMemData->ipc[ii]);
2444 					kk = cdsPciModules.adcCount;
2445 					cdsPciModules.adcType[kk] = GSC_16AI64SSA;
2446 					cdsPciModules.adcConfig[kk] = ioMemData->ipc[ii];
2447 					cdsPciModules.adcCount ++;
2448 					status ++;
2449 				}
2450 				break;
2451 			case GSC_16AO16:
2452 				if((cdsPciModules.cards_used[jj].type == GSC_16AO16) && 
2453 					(cdsPciModules.cards_used[jj].instance == dacCnt))
2454 				{
2455 					printf("Found DAC at %d %d\n",jj,ioMemData->ipc[ii]);
2456 					kk = cdsPciModules.dacCount;
2457 					cdsPciModules.dacType[kk] = GSC_16AO16;
2458 					cdsPciModules.dacConfig[kk] = ioMemData->ipc[ii];
2459 	   				cdsPciModules.pci_dac[kk] = (long)(ioMemData->iodata[ii]);
2460 					cdsPciModules.dacCount ++;
2461 					status ++;
2462 				}
2463 				break;
2464 			case GSC_18AO8:
2465 				if((cdsPciModules.cards_used[jj].type == GSC_18AO8) && 
2466 					(cdsPciModules.cards_used[jj].instance == dacCnt))
2467 				{
2468 					printf("Found DAC at %d %d\n",jj,ioMemData->ipc[ii]);
2469 					kk = cdsPciModules.dacCount;
2470 					cdsPciModules.dacType[kk] = GSC_18AO8;
2471 					cdsPciModules.dacConfig[kk] = ioMemData->ipc[ii];
2472 	   				cdsPciModules.pci_dac[kk] = (long)(ioMemData->iodata[ii]);
2473 					cdsPciModules.dacCount ++;
2474 					status ++;
2475 				}
2476 				break;
2477 			case CON_6464DIO:
2478 				if((cdsPciModules.cards_used[jj].type == CON_6464DIO) && 
2479 					(cdsPciModules.cards_used[jj].instance == doCnt))
2480 				{
2481 					kk = cdsPciModules.doCount;
2482 					printf("Found 6464 DIO CONTEC at %d 0x%x\n",jj,ioMemData->ipc[ii]);
2483 					cdsPciModules.doType[kk] = ioMemData->model[ii];
2484 					cdsPciModules.pci_do[kk] = ioMemData->ipc[ii];
2485 					cdsPciModules.doCount ++;
2486 					cdsPciModules.cDio6464lCount ++;
2487 					cdsPciModules.pci_do[kk] = ioMemData->ipc[ii];
2488 					cdsPciModules.doInstance[kk] = doCnt;
2489 				}
2490 				break;
2491                         case CON_32DO:
2492 		                if((cdsPciModules.cards_used[jj].type == CON_32DO) &&
2493 		                        (cdsPciModules.cards_used[jj].instance == do32Cnt))
2494 		                {
2495 					kk = cdsPciModules.doCount;
2496                			      	printf("Found 32 DO CONTEC at %d 0x%x\n",jj,ioMemData->ipc[ii]);
2497 		                      	cdsPciModules.doType[kk] = ioMemData->model[ii];
2498                                       	cdsPciModules.pci_do[kk] = ioMemData->ipc[ii];
2499                                       	cdsPciModules.doCount ++; 
2500                                       	cdsPciModules.cDo32lCount ++; 
2501 					cdsPciModules.doInstance[kk] = do32Cnt;
2502 				 }
2503 				 break;
2504 			case ACS_16DIO:
2505 				if((cdsPciModules.cards_used[jj].type == ACS_16DIO) && 
2506 					(cdsPciModules.cards_used[jj].instance == doIIRO16Cnt))
2507 				{
2508 					printf("Found Access IIRO-16 at %d 0x%x\n",jj,ioMemData->ipc[ii]);
2509 					cdsPciModules.doType[doCnt] = ioMemData->model[ii];
2510 					cdsPciModules.pci_do[doCnt] = ioMemData->ipc[ii];
2511 					cdsPciModules.doCount ++;
2512 					cdsPciModules.iiroDio1Count ++;
2513 					cdsPciModules.doInstance[kk] = doIIRO16Cnt;
2514 				}
2515 				break;
2516 			default:
2517 				break;
2518 		   }
2519 		}
2520 		if(ioMemData->model[ii] == GSC_16AI64SSA) adcCnt ++;
2521 		if(ioMemData->model[ii] == GSC_16AO16) dacCnt ++;
2522 		if(ioMemData->model[ii] == GSC_18AO8) dacCnt ++;
2523 		if(ioMemData->model[ii] == CON_6464DIO) doCnt ++;
2524 		if(ioMemData->model[ii] == CON_32DO) do32Cnt ++;
2525 		if(ioMemData->model[ii] == ACS_16DIO) doIIRO16Cnt ++;
2526 	}
2527 	// If no ADC cards were found, then SLAVE cannot run
2528 	if(!cdsPciModules.adcCount)
2529 	{
2530 		printf("No ADC cards found - exiting\n");
2531 		return -1;
2532 	}
2533 	// This did not quite work for some reason
2534 	// Need to find a way to handle skipped DAC cards in slaves
2535 	//cdsPciModules.dacCount = ioMemData->dacCount;
2536 #endif
2537 	printf("%d PCI cards found \n",status);
2538 
2539 	// Print out all the I/O information
2540         printf("***************************************************************************\n");
2541 #ifdef ADC_MASTER
2542 		// Master send module counds to SLAVE via ipc shm
2543 		ioMemData->totalCards = status;
2544 		ioMemData->adcCount = cdsPciModules.adcCount;
2545 		ioMemData->dacCount = cdsPciModules.dacCount;
2546 		ioMemData->bioCount = cdsPciModules.doCount;
2547 		// kk will act as ioMem location counter for mapping modules
2548 		kk = cdsPciModules.adcCount;
2549 #if defined (TIME_SLAVE) || defined (RFM_TIME_SLAVE)
2550 		ioMemData->totalCards = 2;
2551 		ioMemData->adcCount = 2;
2552 		ioMemData->dacCount = 0;
2553 		ioMemData->bioCount = 0;
2554 		ioMemData->model[0] = GSC_16AI64SSA;
2555 		ioMemData->ipc[0] = 0;	// ioData memory buffer location for SLAVE to use
2556 		ioMemData->model[1] = GSC_16AI64SSA;
2557 		ioMemData->ipc[1] = 1;	// ioData memory buffer location for SLAVE to use
2558 #endif
2559 #endif
2560 	printf("%d ADC cards found\n",cdsPciModules.adcCount);
2561 	for(ii=0;ii<cdsPciModules.adcCount;ii++)
2562         {
2563 #ifdef ADC_MASTER
2564 		// MASTER maps ADC modules first in ipc shm for SLAVES
2565 		ioMemData->model[ii] = cdsPciModules.adcType[ii];
2566 		ioMemData->ipc[ii] = ii;	// ioData memory buffer location for SLAVE to use
2567 #endif
2568                 if(cdsPciModules.adcType[ii] == GSC_18AISS8AO8)
2569                 {
2570                         printf("\tADC %d is a GSC_18AISS8AO8 module\n",ii);
2571                         if((cdsPciModules.adcConfig[ii] & 0x10000) > 0) jj = 4;
2572                         else jj = 8;
2573                         printf("\t\tChannels = %d \n",jj);
2574                         printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.adcConfig[ii] & 0xfff));
2575                 }
2576                 if(cdsPciModules.adcType[ii] == GSC_16AISS8AO4)
2577                 {
2578                         printf("\tADC %d is a GSC_16AISS8AO4 module\n",ii);
2579                         if((cdsPciModules.adcConfig[ii] & 0x10000) > 0) jj = 4;
2580                         else jj = 8;
2581                         printf("\t\tChannels = %d \n",jj);
2582                         printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.adcConfig[ii] & 0xfff));
2583                 }
2584                 if(cdsPciModules.adcType[ii] == GSC_16AI64SSA)
2585                 {
2586                         printf("\tADC %d is a GSC_16AI64SSA module\n",ii);
2587                         if((cdsPciModules.adcConfig[ii] & 0x10000) > 0) jj = 32;
2588                         else jj = 64;
2589                         printf("\t\tChannels = %d \n",jj);
2590                         printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.adcConfig[ii] & 0xfff));
2591                 }
2592         }
2593         printf("***************************************************************************\n");
2594 	printf("%d DAC cards found\n",cdsPciModules.dacCount);
2595 	for(ii=0;ii<cdsPciModules.dacCount;ii++)
2596         {
2597                 if(cdsPciModules.dacType[ii] == GSC_18AISS8AO8)
2598                 {
2599                         printf("\tDAC %d is a GSC_18AISS8AO8 module\n",ii);
2600                         if((cdsPciModules.dacConfig[ii] & 0x20000) > 0) jj = 0;
2601                         else jj = 4;
2602                         printf("\t\tChannels = %d \n",jj);
2603                         printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.dacConfig[ii] & 0xfff));
2604                 }
2605                 if(cdsPciModules.dacType[ii] == GSC_16AISS8AO4)
2606                 {
2607                         printf("\tDAC %d is a GSC_16AISS8AO4 module\n",ii);
2608                         if((cdsPciModules.dacConfig[ii] & 0x20000) > 0) jj = 0;
2609                         else jj = 4;
2610                         printf("\t\tChannels = %d \n",jj);
2611                         printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.dacConfig[ii] & 0xfff));
2612                 }
2613                 if(cdsPciModules.dacType[ii] == GSC_18AO8)
2614 		{
2615                         printf("\tDAC %d is a GSC_18AO8 module\n",ii);
2616 		}
2617                 if(cdsPciModules.dacType[ii] == GSC_16AO16)
2618                 {
2619                         printf("\tDAC %d is a GSC_16AO16 module\n",ii);
2620                         if((cdsPciModules.dacConfig[ii] & 0x10000) == 0x10000) jj = 8;
2621                         if((cdsPciModules.dacConfig[ii] & 0x20000) == 0x20000) jj = 12;
2622                         if((cdsPciModules.dacConfig[ii] & 0x30000) == 0x30000) jj = 16;
2623                         printf("\t\tChannels = %d \n",jj);
2624                         if((cdsPciModules.dacConfig[ii] & 0xC0000) == 0x0000)
2625 			{
2626                         	printf("\t\tFilters = None\n");
2627 			}
2628                         if((cdsPciModules.dacConfig[ii] & 0xC0000) == 0x40000)
2629 			{
2630                         	printf("\t\tFilters = 10kHz\n");
2631 			}
2632                         if((cdsPciModules.dacConfig[ii] & 0xC0000) == 0x80000)
2633 			{
2634                         	printf("\t\tFilters = 100kHz\n");
2635 			}
2636                         if((cdsPciModules.dacConfig[ii] & 0x100000) == 0x100000)
2637 			{
2638                         	printf("\t\tOutput Type = Differential\n");
2639 			}
2640                         printf("\t\tFirmware Rev = %d \n\n",(cdsPciModules.dacConfig[ii] & 0xfff));
2641                 }
2642 #ifdef ADC_MASTER
2643 		// Pass DAC info to SLAVE processes
2644 		ioMemData->model[kk] = cdsPciModules.dacType[ii];
2645 		ioMemData->ipc[kk] = kk;
2646 		// Following used by MASTER to point to ipc memory for inputting DAC data from SLAVES
2647                 cdsPciModules.dacConfig[ii]  = kk;
2648 printf("MASTER DAC SLOT %d %d\n",ii,cdsPciModules.dacConfig[ii]);
2649 		kk ++;
2650 #endif
2651 	}
2652         printf("***************************************************************************\n");
2653 	printf("%d DIO cards found\n",cdsPciModules.dioCount);
2654         printf("***************************************************************************\n");
2655 	printf("%d IIRO-8 Isolated DIO cards found\n",cdsPciModules.iiroDioCount);
2656         printf("***************************************************************************\n");
2657 	printf("%d IIRO-16 Isolated DIO cards found\n",cdsPciModules.iiroDio1Count);
2658         printf("***************************************************************************\n");
2659 	printf("%d Contec 32ch PCIe DO cards found\n",cdsPciModules.cDo32lCount);
2660 	printf("%d Contec PCIe DIO1616 cards found\n",cdsPciModules.cDio1616lCount);
2661 	printf("%d Contec PCIe DIO6464 cards found\n",cdsPciModules.cDio6464lCount);
2662 	printf("%d DO cards found\n",cdsPciModules.doCount);
2663 #ifdef ADC_MASTER
2664 	// MASTER sends DIO module information to SLAVES
2665 	// Note that for DIO, SLAVE modules will perform the I/O directly and therefore need to
2666 	// know the PCIe address of these modules.
2667 	ioMemData->bioCount = cdsPciModules.doCount;
2668 	for(ii=0;ii<cdsPciModules.doCount;ii++)
2669         {
2670 		// MASTER needs to find Contec 1616 I/O card to control timing slave.
2671 		if(cdsPciModules.doType[ii] == CON_1616DIO)
2672 		{
2673 			tdsControl[tdsCount] = ii;
2674 			printf("TDS controller %d is at %d\n",tdsCount,ii);
2675 			tdsCount ++;
2676 		}
2677 		ioMemData->model[kk] = cdsPciModules.doType[ii];
2678 		// Unlike ADC and DAC, where a memory buffer number is passed, a PCIe address is passed
2679 		// for DIO cards.
2680 		ioMemData->ipc[kk] = cdsPciModules.pci_do[ii];
2681 		kk ++;
2682 	}
2683 	printf("Total of %d I/O modules found and mapped\n",kk);
2684 #endif
2685         printf("***************************************************************************\n");
2686 // Following section maps Reflected Memory, both VMIC hardware style and Dolphin PCIe network style.
2687 // Slave units will perform I/O transactions with RFM directly ie MASTER does not do RFM I/O.
2688 // Master unit only maps the RFM I/O space and passes pointers to SLAVES.
2689 
2690 #ifdef ADC_SLAVE
2691 	// Slave gets RFM module count from MASTER.
2692 	cdsPciModules.rfmCount = ioMemData->rfmCount;
2693 	cdsPciModules.dolphinCount = ioMemData->dolphinCount;
2694 	cdsPciModules.dolphin[0] = ioMemData->dolphin[0];
2695 	cdsPciModules.dolphin[1] = ioMemData->dolphin[1];
2696 #endif
2697 	printf("%d RFM cards found\n",cdsPciModules.rfmCount);
2698 #ifdef ADC_MASTER
2699 	ioMemData->rfmCount = cdsPciModules.rfmCount;
2700 #endif
2701 	for(ii=0;ii<cdsPciModules.rfmCount;ii++)
2702         {
2703                  printf("\tRFM %d is a VMIC_%x module with Node ID %d\n", ii, cdsPciModules.rfmType[ii], cdsPciModules.rfmConfig[ii]);
2704 #ifdef ADC_SLAVE
2705 		cdsPciModules.pci_rfm[ii] = ioMemData->pci_rfm[ii];
2706 		cdsPciModules.pci_rfm_dma[ii] = ioMemData->pci_rfm_dma[ii];
2707 #endif
2708 		printf("address is 0x%x\n",cdsPciModules.pci_rfm[ii]);
2709 #ifdef ADC_MASTER
2710 		// Master sends RFM memory pointers to SLAVES
2711 		ioMemData->pci_rfm[ii] = cdsPciModules.pci_rfm[ii];
2712 		ioMemData->pci_rfm_dma[ii] = cdsPciModules.pci_rfm_dma[ii];
2713 #endif
2714 	}
2715 	ioMemData->dolphinCount = 0;
2716 #ifdef DOLPHIN_TEST
2717 
2718 	ioMemData->dolphinCount = cdsPciModules.dolphinCount;
2719 	ioMemData->dolphin[0] = cdsPciModules.dolphin[0];
2720 	ioMemData->dolphin[1] = cdsPciModules.dolphin[1];
2721 
2722 // Where not all FE computers have an IRIG-B module to tell time, a master and multiple
2723 // slaves may be defined to send/receive GPS time seconds via PCIe RFM. This is only
2724 // for use by ADC_MASTER applications.
2725 #ifdef TIME_MASTER
2726 	rfmTime = (volatile unsigned int *)cdsPciModules.dolphin[1];
2727 	printf("TIME MASTER AT 0x%x\n",(int)rfmTime);
2728 #endif
2729 #ifdef TIME_SLAVE
2730 	rfmTime = (volatile unsigned int *)cdsPciModules.dolphin[0];
2731 	printf("TIME SLAVE AT 0x%x\n",(int)rfmTime);
2732 	printf("rfmTime = %d\n", *rfmTime);
2733 #endif
2734 #ifdef IOP_TIME_SLAVE
2735 	rfmTime = (volatile unsigned int *)cdsPciModules.dolphin[0];
2736 	printf("TIME SLAVE IOP AT 0x%x\n",(int)rfmTime);
2737 	printf("rfmTime = %d\n", *rfmTime);
2738 #endif
2739 #endif
2740         printf("***************************************************************************\n");
2741   	if (cdsPciModules.gps) {
2742 	printf("IRIG-B card found %d\n",cdsPciModules.gpsType);
2743         printf("***************************************************************************\n");
2744   	}
2745 
2746  	//cdsPciModules.adcCount = 2;
2747 
2748 	// Code will run on internal timer if no ADC modules are found
2749 	if (cdsPciModules.adcCount == 0) {
2750 		printf("No ADC modules found, running on timer\n");
2751 		run_on_timer = 1;
2752         	//munmap(_epics_shm, MMAP_SIZE);
2753         	//close(wfd);
2754         	//return 0;
2755 	}
2756 
2757 	// Initialize buffer for daqLib.c code
2758 	printf("Initializing space for daqLib buffers\n");
2759 	daqBuffer = (long)&daqArea[0];
2760  
2761 #ifndef NO_DAQ
2762 	printf("Initializing Network\n");
2763 	numFb = cdsDaqNetInit(2);
2764 	if (numFb <= 0) {
2765 		printf("Couldn't initialize Myrinet network connection\n");
2766 		return -1;
2767 	}
2768 	printf("Found %d frameBuilders on network\n",numFb);
2769 #endif
2770 
2771 #ifdef NO_RTL
2772 
2773 #ifdef SPECIFIC_CPU
2774 #define CPUID SPECIFIC_CPU
2775 #else 
2776 #define CPUID 1
2777 #endif
2778 
2779         pLocalEpics = (CDS_EPICS *)&((RFM_FE_COMMS *)_epics_shm)->epicsSpace;
2780 	int cnt;
2781 	for (cnt = 0;  cnt < 10 && pLocalEpics->epicsInput.burtRestore == 0; cnt++) {
2782         	printf("Epics burt restore is %d\n", pLocalEpics->epicsInput.burtRestore);
2783         	msleep(1000);
2784 	}
2785 	if (cnt == 10) {
2786 		// Cleanup
2787 		remove_proc_entry(SYSTEM_NAME_STRING_LOWER, NULL);
2788 #ifdef DOLPHIN_TEST
2789 		finish_dolphin();
2790 #endif
2791 		return -1;
2792 	}
2793 
2794