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'''--(1. 19インチラックケース発注 with 穴あけ加工)-- ''' '''1. Expansion Chasis 内の配線''' (担当：宮川、due: as soon as possible)

'''2. ADC / DAC interface の配線チェック''' (担当:宮川、準備：辰巳, due:5月の宮川 Caltech 出張)

'''3. Anti-Alias module 1台、Anti-Imaging module １台''' (担当：辰巳、due: 5月末)

'''4. Binary Output Interface & BO NIM module 試作''' (担当：辰巳、due: 5月末)

優先順位付

1. Expansion Chasis 内の配線 (担当：宮川、due: as soon as possible)

2. ADC / DAC interface の配線チェック (担当:宮川、準備：辰巳, due:5月の宮川 Caltech 出張)

3. Anti-Alias module 1台、Anti-Imaging module １台 (担当：辰巳、due: 5月末)

4. Binary Output Interface & BO NIM module 試作 (担当：辰巳、due: 5月末)

CLIO/Tasks/DigitalControl/AnalogFrontEnd2 (last edited 2009-09-17 15:58:46 by whitehole)